Global Word Line Driver Layout for Memory Array Area Reduction
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Solution Overview
Problem
High density memory devices face challenges with complex patterned conductor layers, which reduce manufacturing yield and require significant area for peripheral circuitry, due to the use of global and local word line drivers.
Innovation Solution
The configuration of global word line drivers in a column parallel to array blocks, driving multiple columns of local word line drivers, simplifies conductor layout and reduces area usage, while improving wiring yield by providing a noncritical connection route for local word line drivers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If global word line drivers and local word line drivers are disposed in areas between array blocks, then power distribution efficiency and operation speed are improved, but the area required for peripheral circuitry increases significantly
Solution Approach 1:
The patent repositions global word line drivers from the traditional horizontal arrangement between array blocks to a vertical arrangement in a dedicated column. This dimensional change allows global word line drivers to serve multiple array blocks along the vertical direction, reducing the horizontal footprint and freeing up area between array blocks for other purposes.
Solution Approach 2:
Each global word line driver in the vertical column serves multiple array blocks by driving word lines across multiple rows through vertical interlayer connections. This multi-functional arrangement allows a single global word line driver to control word lines in different array blocks, reducing the total number of drivers needed and minimizing peripheral circuitry area.
2Power
If global word line drivers and local word line drivers are disposed in areas between array blocks, then power distribution is improved, but the complexity of patterned conductor layers increases
Solution Approach 1:
The patent segments the word line driver architecture into distinct functional groups: global word line drivers positioned in a vertical column, local word line drivers positioned adjacent to array blocks, and word line decoders positioned in specific regions. This segmentation allows each component to have a dedicated location with simplified connection requirements, reducing the overall complexity of patterned conductor layers while maintaining efficient power distribution.
Solution Approach 2:
The patent introduces vertical interlayer connections as intermediary conduits between the global word line drivers in the vertical column and the local word line drivers adjacent to array blocks. These intermediary connections provide a structured and simplified routing path for signals, reducing the complexity of direct connections between global and local drivers while maintaining efficient power and signal distribution.
3Adaptability or versatility
If complex patterned conductor layers are used to connect word line drivers to array blocks, then connectivity is achieved, but manufacturing yield is reduced
Solution Approach 1:
By arranging global word line drivers in a vertical column and using vertical interlayer connections, the patent creates a three-dimensional routing structure that simplifies conductor patterns compared to traditional planar arrangements. This vertical dimension provides more straightforward routing paths with fewer turns and connections, reducing manufacturing complexity and improving yield while maintaining full connectivity.
Solution Approach 2:
The segmented architecture with global word line drivers in a vertical column and local word line drivers in dedicated regions creates modular connection patterns. Each segment has well-defined connection rules and simplified routing requirements, making the patterned conductor layers easier to manufacture with higher yield while achieving comprehensive connectivity between all drivers and array blocks.
Data Source
AI summary
A memory device includes a memory array having a plurality of rows and columns of array blocks disposed in array block areas, array blocks including sub-arrays of memory cells arranged in rows and columns with word lines disposed in a patterned gate layer along the rows and one or more patterned conductor layers including bit lines disposed along the columns. A plurality of sets of local word line drivers is arranged in rows and columns disposed adjacent to corresponding array blocks. A set of global word line drivers driving global word lines disposed in an overlying patterned conductor layer over the one or more patterned conductor layers in the array blocks.