Global Write Driver for Memory Array Power Reduction
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Solution Overview
Problem
In computing systems, particularly mobile devices, there is a need to reduce memory die size to lower costs while maintaining performance, as excessive memory circuitry consumes power and increases costs.
Innovation Solution
A memory system with reduced circuitry that includes sub-arrays, sense amplifiers, and write driver circuits, which manage power efficiently by using control signals to read and write data, and employing a write boost control signal to ensure data storage with reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If supporting circuitry in memory is reduced to decrease die size, then cost is reduced, but performance may deteriorate
Solution Approach 1:
The patent merges multiple write driver circuits into a single shared write driver that can service multiple sub-arrays. The write driver is controlled by control logic that determines which sub-array should receive write operations based on address information. This consolidation reduces the number of write drivers needed, decreasing die size and cost while maintaining the ability to perform write operations across multiple sub-arrays, thus preserving performance.
Solution Approach 2:
The single write driver is designed to be universal, capable of driving multiple sub-arrays rather than being dedicated to a single sub-array. The control logic enables the write driver to dynamically switch between different sub-arrays based on the memory access pattern. This multi-functionality allows one write driver to replace what would traditionally require multiple dedicated write drivers, reducing circuitry while maintaining full memory functionality.
2Use of energy by moving object
If supporting circuitry is reduced to extend battery life, then power consumption is reduced, but functionality may be compromised
Solution Approach 1:
The patent combines multiple write driver functions into a single shared write driver circuit that services multiple sub-arrays. This consolidation reduces the total number of active transistors and circuit elements, thereby reducing static power leakage and dynamic power consumption. The control logic coordinates access to ensure the single write driver can efficiently service multiple sub-arrays without compromising the memory's ability to handle write operations to any sub-array.
Solution Approach 2:
The control logic implements periodic or selective activation of the shared write driver based on which sub-arrays need to be written. Rather than having multiple write drivers continuously ready, the single write driver is activated only when needed and for specific time periods corresponding to write operations. This reduces power consumption by minimizing the time circuit elements are in high-power states while maintaining full functionality when write operations are required.
Data Source
AI summary
A system for storing data in a memory may include circuitry that may receive an address, a command and data. The circuitry may also determine a type of the command and generate a read control or write control signal dependent upon the type. The system may also include a plurality of sub-arrays and sense amplifiers. Each of the sub-arrays may include a plurality of memory cells. Each of the sense amplifiers may be coupled to a respective one of the plurality of sub-arrays and may read data stored in a first memory cell included in the respective sub-array. The system may also include one or more write driver circuits. A first write driver circuit may be coupled to at least two of the plurality of sub-arrays. The first write driver circuit may be configured to store data into a second memory cell in one of the at least two sub-arrays.