Selective Glue Layer Etching for Low-Resistance Contact Isolation
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to reduce contact resistance in semiconductor devices, particularly due to the presence of a glue layer at the interfaces between contacts, which degrades device performance.
Innovation Solution
An etching process is performed to remove the glue layer from the bottom surface of contact openings and reduce its thickness on the sidewalls, thereby reducing contact resistance and enhancing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a glue layer is formed at the interfaces between contacts to prevent metal diffusion, then reliability is improved, but contact resistance increases and device performance degrades
Solution Approach 1:
The patent applies local quality by creating a non-uniform glue layer distribution where the glue layer is present on sidewalls for diffusion prevention but removed from bottom surfaces to minimize contact resistance. This spatial variation in glue layer presence allows different regions to serve different functions: sidewall regions provide reliability while bottom regions maintain low contact resistance.
Solution Approach 2:
The patent segments the glue layer into two distinct regions: sidewall glue layer and bottom glue layer. The sidewall glue layer is retained to prevent metal diffusion and ensure reliability, while the bottom glue layer is removed to reduce contact resistance. This segmentation allows the system to simultaneously achieve both reliability and low contact resistance by treating different spatial locations differently.
2Productivity
If feature sizes are decreased to increase functional density, then productivity is improved, but fabrication difficulty increases
Solution Approach 1:
The patent changes the physical parameters of the glue layer through selective etching processes. By controlling etch depth, etch selectivity, and etch conditions, the glue layer thickness is precisely adjusted to be present on sidewalls but removed from bottoms. This parameter control enables the process to work at smaller feature sizes while maintaining fabrication feasibility.
Solution Approach 2:
The patent performs preliminary action by forming the glue layer uniformly first, then selectively removing it from bottom surfaces before contact formation. This preliminary selective removal simplifies subsequent fabrication steps and enables precise control over glue layer distribution, making the overall process more manageable at smaller feature sizes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively decreases contact resistance, leading to improved performance and reliability of semiconductor devices by eliminating the glue layer at critical interfaces.
Implementation Method 1
An etching process is performed to remove the glue layer from the bottom surface of contact openings and reduce its thickness on the sidewalls
Data Source
AI summary
A semiconductor device with reduced contact resistance is provided. The semiconductor device includes a substrate having a channel region and a source/drain region, a source/drain contact structure over the source/drain region, a conductive structure over the source/drain contact structure, an interlayer dielectric (ILD) layer surrounding the conductive structure and source/drain contact structure, a dielectric liner between the ILD layer and the conductive structure, and a diffusion barrier between the dielectric liner and the conductive structure.