Phased-Array Receiver gm-C Circuit Parasitic Capacitance
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Solution Overview
Problem
Conventional wireless phased-array receivers for mm-wave applications face challenges with high parasitic capacitance due to long on-chip interconnects, leading to signal degradation, increased power consumption, and larger chip area, which are not effectively addressed by existing beamforming and low-pass filtering solutions.
Innovation Solution
A circuit design utilizing a g m-C topology with multiple stages of variable gain transconductors and capacitors for phase-shifting and filtering, which accounts for parasitic capacitance to eliminate signal losses and reduce the need for additional amplifiers, implemented in 40 nm CMOS technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If long on-chip interconnects are used to drive signals from separate antennas to the summator, then the receiver can process multiple antenna paths, but parasitic capacitance increases causing signal degradation
Solution Approach 1:
The patent combines the low-pass filter and beamformer into a single integrated circuit block. The filter stages are positioned to receive signals directly from antenna paths without requiring long interconnects to a separate summator, thereby reducing parasitic capacitance while maintaining multi-antenna path processing capability
Solution Approach 2:
The patent reorganizes the signal processing architecture by implementing filtering and beamforming in an analogue baseband dimension rather than at RF. This dimensional change allows signals from multiple antennas to be processed through shared filter stages without requiring long RF interconnects, reducing parasitic effects
2Reliability
If buffers/amplifiers are added to compensate for signal losses from parasitic capacitance, then signal quality is maintained, but power consumption increases
Solution Approach 1:
The patent converts the harmful effect of parasitic capacitance into a beneficial design feature by integrating the low-pass filter stages within the beamformer circuit. The filter stages are positioned to naturally compensate for parasitic effects without requiring additional amplifiers, thereby maintaining signal quality while reducing power consumption
3Reliability
If large capacitors are used in the low-pass filter to meet noise and transfer function requirements, then filtering performance is improved, but chip area increases
Solution Approach 1:
The patent merges the low-pass filter and beamformer into a single integrated circuit. The filter stages share circuit elements and infrastructure with the beamformer, eliminating the need for separate large capacitors and reducing overall chip area while maintaining filtering performance
Solution Approach 2:
The integrated circuit performs multiple functions: low-pass filtering, beamforming, and signal combination. By making the circuit universal and multi-functional, the patent eliminates the need for separate dedicated filter components with large capacitors, thereby reducing chip area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution reduces power consumption, area footprint, and improves dynamic range by eliminating signal losses due to parasitic capacitance, while providing efficient phase-shifting and filtering capabilities for mm-wave applications.
Implementation Method 1
the first stage is arranged for performing phase-shifting of the input signal, thereby producing an intermediate signal
Implementation Method 2
The first stage and second stage together form a filter
Data Source
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AI summary
The present invention relates to a circuit for providing a signal gain, comprising a first stage comprising a first set of variable gain transconductors arranged for performing phase-shifting of an input signal and providing an intermediate signal, and a second stage comprising a second set of transconductors and a plurality of capacitors receiving the intermediate signal and providing an output signal, wherein the first stage and second stage together form a filter, and wherein the first set of variable gain transconductors and at least one of the transconductors from the second set define the signal gain of the circuit. Further, the first stage may comprise multiple first sets of variable gain transconductors arranged for performing beamforming, each set receiving a different input signal and each having outputs connected in parallel, thereby providing a combined intermediate signal. The present disclosure describes a wireless phased-array receiver comprising the proposed circuit.