Parallel GNN Hardware Accelerator for Fast Model Pruning
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Solution Overview
Problem
Existing CPU and GPU-based devices struggle to efficiently train and prune large Graph Neural Networks (GNNs) due to computational demands, leading to prolonged training times and memory occupation, rendering them unavailable for other tasks.
Innovation Solution
A specialized hardware accelerator, such as an FPGA or ASIC-based GNNTP hardware accelerator, employs pruning algorithms like Gradient Signal Preservation (GraSP) to train and prune GNN models, utilizing parallel processing elements and shared memory to efficiently reduce model size and speed up the process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If CPU and GPU based devices are used to train large GNNs, then GNN models can be trained, but training time becomes very long and devices become unavailable for other tasks
Solution Approach 1:
The patent segments the GNN training process by dividing the graph into multiple subgraphs that can be processed in parallel across multiple hardware processing elements. This segmentation enables concurrent training of different graph portions, significantly reducing total training time while maintaining model accuracy.
Solution Approach 2:
The patent introduces a specialized hardware accelerator dimension with custom architecture designed specifically for GNN training. This new dimensional approach with dedicated hardware resources provides performance improvement of 2x to 10x compared to traditional CPU/GPU systems, transforming the training time characteristic.
2Productivity
If CPU and GPU based devices train large GNNs, then GNN models can be trained, but devices occupy large amounts of memory and become unavailable for other tasks
Solution Approach 1:
The patent divides the large GNN model into multiple subgraphs that can be processed and stored separately across multiple hardware processing elements. This segmentation reduces the memory footprint required for any single processing unit while enabling parallel training of the complete model through distributed memory access.
3Loss of time
If specialized hardware accelerator is used to train GNNs, then training time is reduced and model size is reduced, but device complexity increases
Solution Approach 1:
The patent designs the hardware accelerator with multiple parallel hardware processing elements that can collectively handle various GNN training tasks. This multi-functional architecture, combined with shared memory resources, provides the necessary computational power while managing complexity through resource sharing and parallelization.
Data Source
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AI summary
The description relates to graph neural network hardware accelerators. One example can include multiple FPGAs or ASICs that each include multiple parallel arranged processing elements and a shared memory. Individual processing elements are configured to prune a subgraph of a graph neural network model. The shared memory is configured to recombine the pruned subgraphs to generate a pruned graph neural network model.