GNN Hardware Accelerator for Parallel Training and Pruning
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Solution Overview
Problem
Existing CPU and GPU-based devices struggle to efficiently train and prune large Graph Neural Networks (GNNs) due to computational demands, leading to long training times and memory occupation, rendering them unavailable for other tasks.
Innovation Solution
A specialized hardware accelerator, such as an FPGA or ASIC-based GNNTP hardware accelerator, employs pruning algorithms like Gradient Signal Preservation (GraSP) to train and prune GNN models, distributing the workload across parallel hardware processing elements, reducing model size and improving efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If CPU and GPU based devices are used to train and prune large GNNs, then the training and pruning can be performed, but the training time becomes very long and the devices become unavailable for other tasks
Solution Approach 1:
The patent divides the GNN model into multiple subgraphs and distributes them across multiple FPGAs for parallel processing. Each FPGA processes a specific subgraph independently, enabling simultaneous training and pruning operations that significantly reduce total processing time and device unavailability.
Solution Approach 2:
The patent introduces a specialized FPGA-based hardware accelerator as an intermediary between the GNN model and the CPU/GPU devices. This intermediary handles the computationally intensive training and pruning operations, freeing up the original devices for other tasks while maintaining efficient processing through dedicated hardware circuits.
2Reliability
If large GNN models are trained and pruned on existing devices, then the model accuracy can be achieved, but the memory occupation becomes excessive
Solution Approach 1:
The patent segments the large GNN model into smaller subgraphs that can be processed individually on FPGAs. This segmentation reduces the memory footprint required at any given time while maintaining the ability to achieve full model accuracy through distributed parallel processing of all subgraphs.
Solution Approach 2:
The patent extracts the computationally intensive training and pruning operations from the CPU/GPU memory system and implements them in dedicated FPGA hardware circuits. This extraction eliminates the need for excessive memory occupation on general-purpose devices while preserving model accuracy through hardware-accelerated computation.
3Productivity
If specialized hardware accelerators are used to train and prune GNNs, then the training and pruning speed is significantly accelerated, but the device complexity increases
Solution Approach 1:
The patent designs FPGAs with reconfigurable hardware circuits that can perform multiple functions including training, pruning, and inference operations on GNNs. This multi-functionality allows a single hardware accelerator to handle various GNN workloads, reducing the need for multiple specialized devices and simplifying the overall system architecture.
Solution Approach 2:
The patent implements self-service mechanisms where the FPGA hardware accelerator automatically manages the distribution of subgraphs across processing elements, handles memory management for pruned models, and coordinates communication between parallel processing units. This self-service capability reduces the need for complex external control systems while maintaining high training speeds.
Data Source
AI summary
The description relates to graph neural network hardware accelerators. One example can include multiple FPGAs or ASICs that each include multiple parallel arranged processing elements and a shared memory. Individual processing elements are configured to prune a subgraph of a graph neural network model. The shared memory is configured to recombine the pruned subgraphs to generate a pruned graph neural network model.