Graph Neural Network Memory Access via Sequential Node Sampling

Solution Overview

Problem

Graph Neural Networks (GNNs) face inefficiencies in memory access due to random memory accesses and bank conflicts in DDR SDRAM, which hinder performance in processing unstructured graph data.

Innovation Solution

The method involves determining candidate node identifiers that are sequentially stored in memory, allowing for sequential access and using bank counters to balance access across memory banks, thereby reducing bank conflicts and improving memory access efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If graph data is accessed using traditional memory architecture, then node attribute data can be stored in memory, but random memory accesses occur resulting in bank conflicts and reduced memory access efficiency

Engineering Contradiction:

Improvememory access efficiencyVSAvoidbank conflicts

Core Design Contradiction:

ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent segments the memory access process into distinct phases: identifying candidate nodes from the root node, determining their physical addresses, and performing sequential reading. This segmentation allows the system to manage memory access more efficiently by breaking down the complex random access pattern into manageable sequential operations, thereby reducing bank conflicts in DDR SDRAM architecture.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary actions by first identifying candidate nodes and calculating their physical addresses before actually reading the data from memory. This preliminary address calculation and node identification phase allows the subsequent data reading to be performed sequentially rather than randomly, improving memory access efficiency and reducing bank conflicts.

Inventive Principle:

Principle #10Preliminary action

2Loss of time

If candidate node identifiers are sequentially stored in memory, then attribute data can be retrieved in a single read operation, but additional processing is required to determine candidate nodes and their physical addresses

Engineering Contradiction:

Improvememory read operation timeVSAvoidaddress determination processing

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The patent performs preliminary actions by first identifying candidate nodes and calculating their physical addresses before actually reading the data from memory. This preliminary address calculation and node identification phase allows the subsequent data reading to be performed sequentially rather than randomly, improving memory access efficiency and reducing bank conflicts.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary address processor that acts as a mediator between the GNN processor and the memory system. This address processor handles the complex task of determining physical addresses and identifying candidate nodes, thereby simplifying the overall system architecture and reducing the processing burden on the main GNN processor while enabling efficient sequential memory access.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Productivity

If bank counters are used to balance access across memory banks, then bank conflicts are reduced, but additional hardware components and processing steps are required

Engineering Contradiction:

Improvememory access efficiencyVSAvoidmemory architecture

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent implements a feedback mechanism through bank counters that monitor and track the number of accesses to each memory bank. This feedback information is used to dynamically balance the access load across different banks, preventing bank conflicts and improving overall memory access efficiency. The bank counters provide real-time information that guides the address processor in distributing access patterns evenly across available memory banks.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The patent introduces an intermediary address processor that acts as a mediator between the GNN processor and the memory system. This address processor handles the complex task of determining physical addresses and identifying candidate nodes, thereby simplifying the overall system architecture and reducing the processing burden on the main GNN processor while enabling efficient sequential memory access.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS11886352B2Access friendly memory architecture of graph neural network sampling

Publication Date: 2024.01.30 ALIBABA DAMO (HANGZHOU) TECH CO LTD

AI summary

This specification describes methods and systems for accelerating attribute data access for graph neural network (GNN) processing. An example method includes: receiving a root node identifier corresponding to a node in a graph for GNN processing; determining one or more candidate node identifiers according to the root node identifier, wherein attribute data corresponding to the one or more candidate node identifiers are sequentially stored in a memory; and sampling one or more graph node identifiers at least from the one or more candidate node identifiers for the GNN processing.