GNSS Signal Processing Buffer Memory Architecture
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Solution Overview
Problem
Current GNSS receivers require significant processing power, resources, and cost due to dedicated hardware for correlation and tracking, limiting their efficiency and versatility.
Innovation Solution
A signal processing system with a programmable oscillator and buffer memory that samples and aligns GNSS signals with a reference clock, allowing for efficient sampling, accumulation, and asynchronous correlation, reducing resource consumption and enabling shared resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dedicated hardware correlators and signal processing engines are used for GNSS correlation and tracking, then signal processing capability and acquisition speed are improved, but device complexity, cost, and power consumption increase
Solution Approach 1:
The patent implements a single buffer memory structure that serves multiple functions: storing carrier-stripped samples, providing data to multiple correlation channels, and supporting both acquisition and tracking operations. This universal resource eliminates the need for separate dedicated memory structures for each correlation channel, thereby reducing device complexity while maintaining signal processing capability.
Solution Approach 2:
The patent merges multiple correlation channels to share a common buffer memory resource. Instead of having separate memory structures for each correlation channel, the invention combines them into a single buffer that all channels access, reducing overall device complexity and resource requirements while preserving the parallel processing capability needed for high productivity.
2Loss of time
If dedicated hardware correlators are used for each correlation channel, then correlation speed and acquisition time are improved, but cost and device size increase
Solution Approach 1:
The patent enables continuous correlation operations by maintaining a buffer of carrier-stripped samples that can be continuously processed by multiple correlation channels. The buffer ensures that correlation operations can proceed without interruption or repeated sampling, maintaining high acquisition speed while avoiding the need for complex dedicated hardware for each channel.
Solution Approach 2:
The patent performs carrier stripping and sample accumulation in advance, storing the processed samples in a buffer before correlation operations begin. This preliminary processing eliminates the need for real-time carrier stripping during correlation, allowing multiple channels to operate efficiently on pre-processed data without requiring dedicated hardware for each channel's preprocessing functions.
3Productivity
If multiple correlation channels operate in parallel, then signal acquisition speed is improved, but resource consumption and power usage increase
Solution Approach 1:
The patent combines multiple correlation channels to share a single buffer memory resource, reducing the total amount of memory hardware required. By merging the memory resources of multiple channels into one shared buffer, the system reduces power consumption associated with memory operations while maintaining the parallel processing capability that enables fast acquisition.
Solution Approach 2:
The single buffer memory structure serves multiple correlation channels simultaneously, making it a universal resource that replaces what would otherwise require multiple separate memory structures. This multi-functionality reduces the total power consumption of the system compared to having dedicated memory for each channel, while still enabling parallel operation of multiple correlation channels for high acquisition speed.
Data Source
AI summary
A signal processing system and method for a GNSS digital signal wherein a carrier-stripped GNSS signal, is sampled according to a variable rate, determined by the code NCO, and including a timing circuit arranged to generate a timestamp code determining the sampling time of at least one of the samples in the buffer memory. By taking code samples in this way it is possible to transfer the samples asynchronously to a separate processor for the search task to be performed, for example an asynchronous parallel correlator implemented in the same silicon in hardware, or a media processor such as a graphics accelerator implemented in the same device or a separate physical device.