GNSS Receiver Channel Clocks for Lower-Power Signal Processing
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Solution Overview
Problem
Conventional GNSS receivers face challenges in efficiently processing satellite navigation signals at different clock rates and generating various clocks, leading to inefficiencies and increased power consumption due to the need for all channels to operate on the same channel frequency, regardless of the processed signal spectrum width.
Innovation Solution
The proposed system introduces a method where a clock divider generates a 2N×clock signal as a temporary time scale for all channels, allowing the processor to control digital signal phase differences and output coordinates based on digital quadrature signal components, while selecting the appropriate Analog-to-Digital Converter and generating code and carrier frequency signals using a net accumulation signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If all channels operate on the same channel frequency, then the receiver can process signals from multiple satellites, but power consumption increases and processing efficiency decreases
Solution Approach 1:
The receiver channels are divided into groups, with each group operating on its own divided clock frequency (fclk/2, fclk/4, fclk/8, etc.). This segmentation allows channels to operate at lower frequencies matched to their specific signal processing needs, reducing overall power consumption while maintaining the ability to process multiple satellite signals simultaneously.
Solution Approach 2:
The system dynamically assigns different clock division ratios to different channel groups based on their processing requirements. The processor can adjust which channels operate at which clock frequencies, enabling adaptive power management that optimizes the balance between processing efficiency and energy consumption.
2Use of energy by moving object
If channels operate on divided clocks, then power consumption is reduced, but synchronization and control complexity increases
Solution Approach 1:
A clock divider unit serves as an intermediary that generates multiple divided clock frequencies from a single master clock. This intermediary component simplifies the synchronization problem by providing a hierarchical clock structure where all channel groups can be synchronized to the master clock while operating at different frequencies, reducing the overall control complexity.
Solution Approach 2:
The system merges the clock generation function into a single centralized clock divider unit that produces all required divided frequencies. This consolidation eliminates the need for multiple independent clock sources and their associated synchronization circuits, reducing device complexity while enabling power-efficient divided clock operation across channel groups.
3Device complexity
If a single clock frequency is used for all channels, then device complexity is reduced, but processing efficiency for diverse signal spectra decreases
Solution Approach 1:
The receiver channels are divided into groups, with each group operating on its own divided clock frequency (fclk/2, fclk/4, fclk/8, etc.). This segmentation allows channels to operate at lower frequencies matched to their specific signal processing needs, reducing overall power consumption while maintaining the ability to process multiple satellite signals simultaneously.
Solution Approach 2:
The system dynamically assigns different clock division ratios to different channel groups based on their processing requirements. The processor can adjust which channels operate at which clock frequencies, enabling adaptive power management that optimizes the balance between processing efficiency and energy consumption.
Data Source
AI summary
A method for receiving and processing satellite navigation signals includes receiving the navigation signals; converting the navigation signals into digital signals; providing a clock signal to all channels that process the digital signals; generating frequency division signals; selecting a channel frequency division signal from the frequency division signals based on which ADC is used to convert the satellite navigation signals into digital signals; connecting the channel to the ADC; generating code frequency signal and base carrier frequency signal using a net accumulation signal; processing the digital signal in the channel to produce digital quadrature signal components of the digital signal based on the code frequency signal and the base carrier frequency signal; using a tick signal that represents 2N×clock signal as a temporary time scale for control of the channels for determining digital signal phase differences between the channels; and outputting coordinates based on the quadrature components.