Shared Non-Deterministic Bus Arbitration for GNSS Data Transfer
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Solution Overview
Problem
Global navigational satellite systems (GNSS) face challenges when integrated into multi-functional wireless devices, particularly in optimizing GNSS functionality and managing data transfers efficiently within shared memory resources accessed via a non-deterministic bus.
Innovation Solution
Implementing a method that utilizes a shared memory block across functional blocks of a wireless device, prioritizing data transfers based on urgency, and managing memory as a circular buffer to enhance data transfer efficiency and flexibility, while ensuring timely handling of real-time RF data and error management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a shared memory block is used by multiple functional blocks via a non-deterministic bus, then device complexity is reduced and cost is lowered, but data transfer reliability and timing predictability deteriorate
Solution Approach 1:
The patent implements dynamic priority-based arbitration for bus access, where the RF subsystem can be assigned higher priority when real-time data transfer is required. This dynamic adjustment of access priorities ensures that critical RF data transfers are not blocked by other functional blocks, maintaining reliability while sharing the bus resource.
Solution Approach 2:
The patent introduces a bus arbitration mechanism as an intermediary that manages access requests from multiple functional blocks to the shared memory. This mediator resolves conflicts by allocating bus access rights based on predefined or dynamic priorities, ensuring that critical RF operations receive timely access while other blocks share the resource efficiently.
2Ease of manufacture
If memory access is via a non-deterministic bus shared with other bus masters, then manufacturing cost is reduced, but data transfer speed and timing precision deteriorate
Solution Approach 1:
The system dynamically adjusts bus access priorities based on the operational state of the RF subsystem. When the RF subsystem requires high-speed data transfer, it is granted higher priority access to the shared memory, ensuring that critical data operations maintain high speed despite sharing the bus with other functional blocks.
Solution Approach 2:
The patent implements preliminary priority assignment where the RF subsystem is pre-configured with high-priority access rights for time-critical operations. This preliminary setup ensures that when real-time data transfer is needed, the RF subsystem can immediately access the shared memory without waiting for lower-priority blocks, maintaining high transfer speeds.
3Reliability
If discrete memory subcomponents are included in each functional block, then data transfer reliability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent merges memory resources into a single shared memory block that serves multiple functional blocks including the RF subsystem, GPS, and other wireless technologies. This consolidation reduces the total number of memory components in the system while maintaining reliable data transfer through priority-based access control that ensures critical RF operations have guaranteed access.
Solution Approach 2:
The shared memory block is designed as a universal resource that can serve multiple functional blocks with different data transfer requirements. The memory itself is multi-functional, supporting both high-speed RF data transfers and lower-priority operations from other blocks, thereby reducing overall system complexity while maintaining reliability through intelligent access management.
4Productivity
If priority-based data transfer is implemented for RF subsystem, then data transfer throughput is improved, but device complexity increases
Solution Approach 1:
The priority control mechanism is implemented dynamically rather than through complex static logic. The system can adjust priorities in real-time based on operational conditions, allowing high throughput for RF operations when needed while simplifying control for other blocks during non-critical periods, thereby improving productivity without proportionally increasing complexity.
Data Source
AI summary
System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.