GNSS Receiver FFT Sharing via Hypothesis Scheduling
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Solution Overview
Problem
Existing GNSS receivers face challenges in efficiently acquiring high complexity GNSS signals due to limited hardware resources and inefficient signal processing techniques.
Innovation Solution
A GNSS receiver design incorporating a multiplexer circuit, FFT circuit, pre-sampler circuit, code generator circuit, and hypothesis scheduling machine (HSM) that enables hardware sharing and coordinated signal processing to efficiently acquire high complexity signals like GPS L5, BeiDou B2a/b, Galileo E5a/b, E6, and Quasi-Zenith Satellite System L6, with features such as Doppler compensation and real-time signal processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional GNSS receiver design is used, then hardware resources are sufficient for basic signals, but acquisition efficiency for high complexity signals is insufficient
Solution Approach 1:
The receiver divides the signal processing task into distinct segments: pre-sampling, correlation, and post-processing. The pre-sampler circuit performs preliminary processing before correlation, and the correlation results are processed in separate post-processing stages, enabling efficient handling of high complexity signals through segmented computation
Solution Approach 2:
The pre-sampler circuit performs preliminary sampling and processing actions before the main correlation operation. By preparing the signal in advance through pre-sampling, the system reduces the computational burden during correlation and improves overall acquisition efficiency for high complexity signals
2Productivity
If separate dedicated hardware is provided for each processing function, then processing capability is sufficient, but hardware resources are wasted and device complexity increases
Solution Approach 1:
The FFT circuit is designed as a universal resource that serves multiple functions: it processes signals from different satellite systems (GPS, BeiDou, Galileo, QZSS), handles different signal complexities, and performs both correlation and spectral analysis. This multi-functional design eliminates the need for separate dedicated hardware for each processing function
Solution Approach 2:
The receiver employs dynamic resource allocation where the FFT circuit and other processing units can be activated or deactivated based on the current signal processing requirements. The hypothesis scheduling machine dynamically manages hardware resources, allocating them to different processing tasks as needed, thereby improving hardware utilization efficiency
3Measurement precision
If high complexity GNSS signals are processed with existing hardware, then signal accuracy is maintained, but power consumption increases
Solution Approach 1:
The receiver uses periodic pre-sampling operations followed by periodic correlation operations. By breaking the processing into periodic cycles where pre-sampling is performed only when needed and correlation is executed efficiently, the system maintains signal processing accuracy while reducing overall power consumption compared to continuous high-complexity processing
Data Source
AI summary
A global navigation satellite system (GNSS) receiver includes a multiplexer circuit, a fast Fourier transform (FFT) circuit, a pre-sampler circuit, a code generator circuit, and a hypothesis scheduling machine (HSM). The multiplexer circuit has a first input port, a second input port, and an output port. The FFT circuit is coupled to the output port. The pre-sampler circuit generates and outputs a data sequence output to the first input port of the multiplexer circuit. The code generator circuit generates and outputs a local replica output to the second input port of the multiplexer circuit. The HSM is coupled to the multiplexer circuit, the pre-sampler circuit, and the code generator circuit. Under coordination of the HSM, the FFT circuit is shared between the pre-sampler circuit and the code generator circuit through the multiplexer circuit.