GNSS PRN Delay Generator With Selectable Enable Frequency
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Solution Overview
Problem
The increase in the number of tracking channels in GNSS receivers for improved precision leads to significant silicon area occupation due to the need for multiple PRN delayed sequence generators, which is not flexible with respect to clock frequency variations.
Innovation Solution
A GNSS receiver apparatus with a configurable PRN delayed sequence generator using shift registers and flip-flops, where the enable frequency of the flip-flops is selectable and can be equal to or greater than the code frequency, allowing flexible operation and reducing the need for additional flip-flops with clock frequency changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of tracking channels is increased to improve precision, then tracking accuracy is improved, but silicon area occupation increases significantly
Solution Approach 1:
The PRN delayed sequence generator is designed to serve multiple tracking channels simultaneously through a shared architecture. The generator uses a single set of shift registers and flip-flops that can be configured to support multiple channels, eliminating the need for separate generators for each channel and thereby reducing silicon area while maintaining tracking precision.
Solution Approach 2:
Multiple PRN delayed sequence generators are merged into a single shared generator unit. The invention combines the functionality of multiple generators into one unified structure that can service multiple tracking channels, reducing the overall silicon area occupied by integrating common resources rather than duplicating components for each channel.
2Adaptability or versatility
If fixed number of flip-flops is used in PRN delayed sequence generator, then device complexity is reduced, but adaptability to clock frequency variations is lost
Solution Approach 1:
The PRN delayed sequence generator employs dynamic configuration capabilities where the number and arrangement of flip-flops can be adjusted based on operational requirements. The generator allows dynamic reconfiguration of the delay structure to adapt to different clock frequencies and tracking channel demands, providing flexibility without permanently increasing device complexity.
Solution Approach 2:
The invention enables parameter changes in the generator structure, specifically allowing the number of flip-flops and their configuration to be modified according to clock frequency variations. This parameter adaptability lets the system optimize performance for different operating conditions while managing complexity through controlled configurability rather than fixed rigid design.
Data Source
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AI summary
A GNSS (Global Navigation Satellite System) receiver apparatus, said receiver (100) comprising a tracking module (5), comprising at least one tracking channel (TRKi) comprising a bank of correlators (25) receving in-phase (Iw) and quadrature (Qw) versions of a received signal (IT; QT), a GNSS Pseudo Random Noise sequence generator (23) generating a Pseudo Random Noise sequence (PS) at a code frequency (Fchip) set by a code Numerical Controlled Oscillator (32) comprised in the tracking channel (TRKi) determining a code rate, a GNSS Pseudo Random Noise delayed sequence generator (24; 44) configured to generate, on the basis of a Pseudo Random Noise sequence (PS) received from said GNSS Pseudo Random Noise sequence generator (23), at least one punctual (P), one early (E1, E2; E1...EK) and one delayed (L1, L2; L1...LK) replica of said Pseudo Random Noise sequence (PS), said GNSS Pseudo Random Noise delayed sequence generator (24; 44) comprising at least a first and second delay lines arranged as shift registers (245, 246; 441, 445), comprising a determined number (N) of flip-flops (FF0...FF15, FF16...FF31; FF0...FFN-1, FFN...FF2N-1) arranged in series and identifying taps at their output and said Pseudo Random Noise sequence (PS) being brought as input of the first register (245; 441), taps of said registers (245, 246; 441, 445) being selected as early (E1, E2; E1...EK) and delayed (L1, L2; L1...LK) replicas of said Pseudo Random Noise sequence (PS) on the basis of selection signal issued by a control logic (41) of the receiver (100), The apparatus comprises a circuit arrangement (32, 36, 37; 32, 42, 43, 45) configured to generate an enable signal (EN) fed to an enable input of said flip-flops (FF0...FF15, FF16...FF31; FF0...FFN-1, FFN...FF2N-1), said enable signal (EN) operating at a selectable enable frequency (1/T_en).