GOA Circuit AC Signal Pull-Down Transistor

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Solution Overview

Problem

Conventional GOA circuits face heating issues due to large capacitance on the clock signal line, which reduces the lifetime of components and introduces reliability concerns, especially in high-resolution or high-refreshing frequency products.

Innovation Solution

A GOA circuit design that replaces the conventional clock signal with an AC signal, featuring high and low voltage levels with reversed phases, reducing the size of the pull-up transistor and alleviating heating by using a pull-down module to manage voltage levels, thereby enhancing stability and lifetime.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the pull-up transistor is made large to drive the scan line and achieve the corresponding falling time, then the scan signal output performance is improved, but the capacitance of the clock signal line becomes large, causing increased current and heating

Engineering Contradiction:

Improvefalling time of scan signalVSAvoidheating of clock signal line

Core Design Contradiction:

SpeedVSTemperature

Solution Approach 1:

The patent introduces a pull-down transistor that actively pulls down the clock signal line during the blank time, inverting the conventional approach of only pulling up the signal. This active pulling down reduces the required capacitance of the clock signal line, thereby reducing the current and heating while maintaining the scan signal output performance

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The patent applies periodic blank time intervals in the scan signal where the pull-down transistor actively pulls down the clock signal line. This periodic action allows the system to reset and reduce voltage levels, decreasing the effective capacitance and current requirements, thus reducing heating while maintaining signal integrity during active periods

Inventive Principle:

Principle #19Periodic action

2Speed

If the pull-up transistor is made large to achieve the corresponding falling time, then the scan signal output performance is improved, but the size of the transistor increases

Engineering Contradiction:

Improvefalling time of scan signalVSAvoidsize of pull-up transistor

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

Instead of relying solely on a large pull-up transistor to achieve the desired falling time, the patent introduces a pull-down transistor that actively pulls down the signal during blank time. This inverted approach allows the use of a smaller pull-up transistor while maintaining signal performance through the complementary action of the pull-down transistor

Inventive Principle:

Principle #13The other way round (Inversion)

3Temperature

If the capacitance of the clock signal line is reduced, then the current and heating are decreased, but the ability to drive the scan line effectively is compromised

Engineering Contradiction:

Improveheating of clock signal lineVSAvoidscan line driving capability

Core Design Contradiction:

TemperatureVSProductivity

Solution Approach 1:

The patent introduces a pull-down transistor that actively pulls down the clock signal line during blank time, compensating for the reduced capacitance. This active pulling down ensures that the scan line can be effectively driven with smaller capacitance, maintaining productivity while reducing heating

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The pull-down transistor acts as an intermediary that facilitates the driving of the scan line with reduced capacitance. By actively managing the voltage levels during blank time, it ensures that the reduced capacitance does not compromise the scan line driving capability, thus maintaining productivity while reducing heating

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS11837188B2Goa circuit and display panel for reducing threshold voltage shift of transistor by pulling down signal during blank time of scan signal

Publication Date: 2023.12.05 TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO LTD

AI summary

A GOA circuit and a display panel are provided. The GOA circuit includes a plurality of GOA units connected in series. Each GOA unit includes a pull-up control module, a pull-up module, a download module, a pull-down maintaining module, a pull-down module, and a bootstrap capacitor. An AC signal applied to the pull-up module has high and low voltage levels. The high voltage level of the AC signal could reduce the rising time and the falling time of the conventional clock signal such that the output of the scan signal could be better. The low voltage level of the AC signal could pull down the signal in the blank time to perform a stress recovery such that the threshold voltage shift of the transistor caused by the high voltage level stress is reduced. This could raise the stability and the lifetime of the circuit.