GOA Array Substrate ESD Defect Reduction via Active Layer Extraction
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Solution Overview
Problem
The integration of gate drive circuits on TFT substrates in GOA technology leads to ElectroStatic Discharge (ESD) defects, causing abnormal displays and high defect rates due to the conductivity of semiconductor materials under high temperatures and intensive wiring, particularly at the intersections of gate and source/drain wires.
Innovation Solution
The design modifies the GOA unit layout by removing the active semiconductor layer at the intersections of gate and source/drain wires and introducing a discharge-inducing region with dummy electrodes, which redirects static electricity away from the active areas, reducing the likelihood of ESD occurrences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the gate drive circuit is integrated on the TFT substrate using GOA technology, then the integration level of the LCD panel is improved and the usage rate of gate drive IC is reduced, but ESD defects occur at wire intersection areas, reducing yield rate
Solution Approach 1:
The patent extracts and removes the active layer from the wire intersection areas where ESD defects occur. By taking out the semiconductor material from these critical regions, the design eliminates the formation of parasitic transistors that cause electrostatic discharge, thereby maintaining high integration levels while improving yield rate.
Solution Approach 2:
The patent applies local quality by differentiating the structure at wire intersection areas from the rest of the active area. Specifically, the active layer is selectively removed only at intersection points while preserving it in functional regions, creating localized structural differences that prevent ESD without compromising overall circuit functionality.
2Manufacturing precision
If intensive wiring is used to meet high PPI and narrow bezel requirements, then display resolution and bezel size are improved, but the probability of ESD at wire intersection areas increases
Solution Approach 1:
The patent extracts the active layer from wire intersection areas to eliminate parasitic transistor formation. This removal prevents ESD events that would otherwise be triggered by the intensive wiring required for high PPI displays, allowing dense routing without proportionally increasing ESD risk.
Solution Approach 2:
The patent converts the harmful effect of wire intersections (which create ESD risk) into a beneficial design feature by intentionally creating ESD-resistant structures at these locations. The modified intersection areas become discharge-safe zones that can handle the intensive wiring density required for high-resolution displays.
3Ease of operation
If the semiconductor pad layer is used as a climbing layer for gate and source, then circuit connectivity is improved, but the conductivity increase under high temperature induces electrostatic discharge
Solution Approach 1:
The patent removes the active layer from wire intersection areas where the semiconductor pad layer would otherwise form parasitic transistors. This extraction prevents the temperature-induced conductivity increase from creating ESD pathways, while the pad layer retains its connectivity function in non-intersection areas.
Solution Approach 2:
The patent applies local quality by preserving the semiconductor pad layer's climbing function in areas where it is needed for connectivity, while selectively removing it only at wire intersection points. This creates localized structural differences that maintain circuit connectivity while eliminating ESD generation at critical locations.
Data Source
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AI summary
The present invention relates to an array substrate, which comprises: a display region and a drive circuit region; the drive circuit region comprises GOA units, the GOA unit comprising a substrate, a gate electrode layer, an insulation layer, an active layer and a source/drain electrode layer, and the drive circuit region further comprises a gate wire connecting to the gate electrode layer, and a source/drain layer wire at the same layer with the source/drain electrode layer, wherein the area between the portions of the gate wire and the source/drain layer wire which intercross with each other is only formed with the insulation layer. The invention further relates to a manufacturing method of an array substrate and a display apparatus comprising the array substrate.