GOA Array Substrate with Variable Transistor Sizes

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Solution Overview

Problem

Existing Gate on Array (GOA) circuits experience uneven charging of display panels due to inconsistent rising and falling times of scan signals across cascaded stages, caused by transmission loss and RC delay in clock signal lines.

Innovation Solution

The design includes an array substrate with cascaded GOA units and clock signal lines, where the size of output transistors increases along the signal transmission direction, and clock signal lines decrease in width, ensuring consistent scan signal output across stages, using low temperature poly-silicon or semiconductor oxide thin-film transistors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the size of output transistors is kept uniform across all GOA stages, then the manufacturing process is simple, but the scan signals exhibit inconsistent rising and falling times due to transmission loss and RC delay

Engineering Contradiction:
Improveuniformity of transistor sizeVSAvoidconsistency of scan signal timing
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent applies local quality by making the output transistor sizes non-uniform across different GOA stages. Specifically, transistors in later stages (which suffer from cumulative transmission loss) are made larger than those in earlier stages. This local variation in transistor size compensates for the cumulative RC delay and transmission loss in clock signal lines, ensuring that all stages produce scan signals with consistent rising and falling times.

Inventive Principle:
Principle #3Local quality

2Reliability

If the size of output transistors is increased to compensate for transmission loss, then the scan signal timing consistency improves, but the device area increases

Engineering Contradiction:
Improveconsistency of scan signal timingVSAvoidarea of array substrate
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent applies local quality by making the output transistor sizes non-uniform across different GOA stages. Specifically, transistors in later stages (which suffer from cumulative transmission loss) are made larger than those in earlier stages. This local variation in transistor size compensates for the cumulative RC delay and transmission loss in clock signal lines, ensuring that all stages produce scan signals with consistent rising and falling times.

Inventive Principle:
Principle #3Local quality

3Area of stationary object

If the width of clock signal lines is reduced to save space, then the manufacturing cost decreases, but the transmission loss and RC delay increase

Engineering Contradiction:
Improvearea occupied by clock signal linesVSAvoidsignal transmission quality
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent applies parameter changes by systematically varying the width of clock signal lines across different stages. The clock signal line width is made smaller in earlier stages and progressively larger in later stages. This parameter variation compensates for the cumulative transmission loss and RC delay that accumulate as signals propagate through multiple stages, ensuring that all stages receive clock signals with sufficient strength and timing accuracy.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11881188B2Array substrate including stages of gate array units having different sized output transistors, and display panel
Publication Date: 2024.01.23 SHENZHEN CHINA STAR OPTOELECTRONICS SEMICON DISPLAY TECH CO LTD
  • US11881188B2 patent drawing
  • US11881188B2 patent drawing
  • US11881188B2 patent drawing

AI summary

A array substrate includes a plurality of stages of cascaded GOA units and a plurality of corresponding clock signal lines electrically connected to them. Each stage of GOA units includes a first output transistor. In the plurality of stages of GOA units, the plurality of first output transistors increase in size along a predetermined direction. The predetermined direction is a signal transmission direction of any of the clock signal lines.