GOA Array Substrate Voltage Signal Line Layering
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Solution Overview
Problem
Existing gate driver on array (GOA) technologies face challenges in minimizing circuit area to achieve narrower frames and improve screen ratio in display panels, limiting design choices and product competitiveness.
Innovation Solution
The proposed array substrate incorporates a GOA driving circuit with thin film transistors, where voltage signal lines are placed above the common line region, reducing the non-display area by avoiding horizontal positioning, and featuring a specific layout with multiple thin film transistors and metal layers to optimize circuit design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If voltage signal lines are placed on the same layer as the common line, then routing is simplified, but the non-display region area increases
Solution Approach 1:
The patent applies dimensionality change by moving voltage signal lines from the same layer as the common line to a different layer (above the second insulating layer). This vertical separation in the Z-dimension allows both the common line and voltage signal lines to coexist without horizontal positioning conflicts, thereby reducing the non-display region area while maintaining routing simplicity through structured layering.
Solution Approach 2:
The patent segments the signal routing into different functional layers: the common line is placed on one layer while voltage signal lines are placed on another layer above the second insulating layer. This segmentation allows independent optimization of each signal type's path and reduces spatial interference, effectively minimizing the non-display region while maintaining routing organization.
2Area of stationary object
If the GOA circuit area is reduced to achieve narrower frames, then screen ratio improves, but circuit design becomes more constrained
Solution Approach 1:
By utilizing vertical layering to place voltage signal lines above the second insulating layer rather than constraining all signals to the same plane, the patent reduces the horizontal footprint of the GOA circuit. This dimensional transition enables narrower frames and improved screen ratio while maintaining design flexibility through three-dimensional spatial arrangement.
3Area of stationary object
If voltage signal lines are positioned above the second insulating layer, then non-display region area is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent implements voltage signal lines on a higher layer above the second insulating layer, utilizing the vertical dimension to reduce horizontal space occupation. This layered approach, while adding manufacturing steps, follows standard thin-film transistor fabrication processes and provides systematic routing that can be integrated into existing manufacturing workflows.
Data Source
AI summary
The array substrate comprises: a substrate including a first region, a second region, and a third region; a first metal layer is disposed on the substrate and forms a gate metal and a common line; a first insulating layer is disposed on the substrate and the first metal layer; a second metal layer is disposed on the first insulating layer and forms a source/drain metal; a second insulating layer is disposed on the first insulating layer and the second metal layer; and a third metal layer is disposed on the second insulating layer and forms a voltage signal line.