GOA Circuit Capacitor Formation via Metal Layer Integration
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Solution Overview
Problem
Existing display technologies with narrow frames face limitations in further reducing the frame width due to the requirement of a large capacitor area in Gate Driver on Array (GOA) circuits, which restricts the size of the GOA circuit and hence the frame's narrowness.
Innovation Solution
The configuration of the array substrate includes a GOA circuit area with at least one first via and one second via, where a data-line metal layer is connected to one electrode and a gate-line metal layer is connected to another electrode through these vias, forming a capacitor without the need for a separate capacitor area, thereby reducing the overall length of the GOA circuit and the frame width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate capacitor area is provided in the GOA circuit, then the capacitor can remove noise and ensure stability, but the length of the GOA circuit increases and the frame width cannot be further reduced
Solution Approach 1:
The patent merges the capacitor function with the data line and gate line structures by forming the capacitor between the data line metal layer and gate line metal layer that already exist in the GOA circuit. This integration eliminates the need for a separate capacitor area while maintaining the noise removal and stability functions of the capacitor.
Solution Approach 2:
The data line and gate line structures serve dual purposes: they perform their primary function of signal transmission and simultaneously function as the capacitor electrodes for noise filtering. This multi-functionality reduces the overall circuit length while maintaining reliability.
2Reliability
If the capacitor area is made large enough to meet capacitor specifications, then the capacitor function is achieved, but the GOA circuit size is limited and frame width cannot be further narrowed
Solution Approach 1:
The patent combines the capacitor structure with the existing data line and gate line, utilizing their spatial relationship to form the capacitor. This merging allows the capacitor to meet specification requirements without occupying additional area, as it uses the space between existing conductive layers.
Solution Approach 2:
The patent transitions from a planar capacitor layout to a three-dimensional structure by forming the capacitor between different metal layers (data line metal layer and gate line metal layer) separated by an insulating layer. This vertical arrangement in another dimension achieves the required capacitance without increasing the horizontal area of the GOA circuit.
Data Source
AI summary
An array substrate includes a GOA circuit area and a display area, the GOA circuit area includes a TFT area and a lead-wire area, the display area includes a data line and a gate line. The GOA circuit area is provided with at least one first via and at least one second via, a data-line metal layer is disposed at the bottom of the at least one first via, and a gate-line metal layer is disposed at the bottom of the at least one second via. The GOA circuit area further includes a first electrode and a second electrode, the data-line metal layer is electrically connected to one electrode through the at least one first via, the gate-line metal layer is electrically connected to the other electrode through the at least one second via, such that a capacitor is formed between the first electrode and the second electrode.