Gate Driver on Array Circuit Preventing DC Path Burnout
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Solution Overview
Problem
The existing gate driver on array (GOA) circuits are prone to instability and failure due to the susceptibility of transistors to long-term pressure and the formation of direct current channels, which can lead to the burning out of inverting circuits and ineffective operation.
Innovation Solution
The proposed GOA circuit includes a pull-up control module, an inverting control module, a first pull-down module, a second pull-down module, and a pull-down maintenance module, which utilize specific transistor configurations and capacitor connections to control voltage levels and prevent direct current channels, ensuring stable operation by maintaining opposite voltage levels between nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the transistor T110 is always turned on to maintain the inverting circuit function, then the voltage level opposition between pull-up node and pull-down node is maintained, but the transistor becomes susceptible due to long-term pressure and may form direct current channels causing burnout
Solution Approach 1:
The patent applies periodic action by controlling transistor T110 to operate in periodic cycles rather than continuously. The transistor is turned on during the pull-up phase and turned off during the pull-down maintenance phase, creating a periodic on-off operation pattern. This is achieved through the timing control circuit that coordinates the clock signal phases, allowing the transistor to rest during certain periods and avoid long-term pressure susceptibility while maintaining its inverting circuit function when needed.
2Reliability
If the clock signal voltage level transitions from high to low to pull down the pull-down node, then the pull-down function is activated, but the transistors are not completely turned off causing the pull-down maintenance circuit to fail
Solution Approach 1:
The patent introduces an intermediary mechanism through the coordinated control of multiple transistors (T110, T130) and the timing control circuit. Instead of relying solely on the clock signal voltage transition to turn off transistors T110 and T130, the system uses the phase difference between clock signals and the interlocking control logic to ensure complete transistor shutdown. The timing control circuit acts as an intermediary that monitors and ensures both transistors are fully off before activating the pull-down maintenance function, preventing voltage level control precision failures.
Solution Approach 2:
The patent applies beforehand cushioning by designing the circuit to anticipate and prevent the failure mode before it occurs. The timing control circuit is configured to ensure that transistors T110 and T130 are completely turned off before the pull-down maintenance phase begins. This preventive measure cushions against the potential failure where incomplete transistor shutdown would cause the pull-down maintenance circuit to malfunction, ensuring reliable operation by addressing the issue before it can manifest.
3Reliability
If a direct current channel forms between constant high voltage terminal and constant low voltage terminal when pull-up node is at high voltage level, then the inverting circuit may be burnt out, but preventing this requires additional control mechanisms
Solution Approach 1:
The patent prevents direct current channel formation by implementing periodic action through phase-differential clock signal control. The transistor controlling the high voltage path is activated only during the pull-up phase when the clock signal is at a specific phase, and is turned off during the pull-down maintenance phase when the opposite-phase clock signal is active. This periodic on-off operation based on clock signal phases eliminates the possibility of continuous direct current flow between high and low voltage terminals, thereby preventing circuit burnout without requiring complex additional control mechanisms.
Data Source
AI summary
A GOA circuit and a display panel are proposed. An inverting control module controls the voltage level of the first node to be opposite to the voltage level of the second node under the control of an (n+1)th-stage clock signal, so that a DC path between a constant high voltage terminal and a first constant low voltage terminal is not formed. When a first node is at the low voltage level, the voltage applied on the second node transitions from the low voltage level to high voltage level. Accordingly, the second node is constantly at the high voltage level at the pull-down maintenance stage in the GOA circuit, and the nth-stage gate-driven signal terminal is still at the low voltage level. In this way, the GOA circuit will not become ineffective.