GOA Circuit High Temperature Stability via Duty Cycle Control
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Solution Overview
Problem
The high temperature stability of Gate Driver on Array (GOA) circuits in tablet displays is compromised due to increased leakage current in thin film transistors, affecting the output waveform and reliability.
Innovation Solution
The GOA circuit design incorporates additional thin film transistors and a specific configuration of pull-up, pull-down, and transfer parts, along with a boast capacitor, to manage clock signals and voltage levels, reducing leakage current and enhancing stability. This includes using thin film transistors connected in a manner that compensates for leakage currents and alternately charges circuit points with lower frequency clock signals to maintain high voltage during non-charge times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If GOA circuit uses thin film transistors for driving horizontal scan lines, then manufacturing cost is reduced and integration is improved, but leakage current increases at high temperature affecting output stability
Solution Approach 1:
The patent introduces a duty cycle control mechanism for the clock signal driving the thin film transistor. By adjusting the duty cycle parameter (ratio of high level time to total period) of the clock signal, the patent optimizes the charging and discharging characteristics of the scan line, reducing the impact of leakage current at high temperatures while maintaining the GOA circuit's manufacturing advantages.
Solution Approach 2:
The patent employs periodic clock signals with specific duty cycles to control the thin film transistor switching. The periodic activation and deactivation of the transistor through controlled duty cycle timing allows the circuit to compensate for leakage effects by ensuring complete charging during high periods and proper discharging during low periods, thereby maintaining output stability at elevated temperatures.
2Ease of manufacture
If thin film transistor leakage current increases at high temperature, then output waveform becomes abnormal, but external IC cannot be used to avoid this issue
Solution Approach 1:
The patent modifies the operational parameters of the thin film transistor by controlling the duty cycle of the clock signal. This parameter adjustment ensures that the transistor has sufficient time to charge the scan line to the required voltage level before being turned off, compensating for the leakage current that occurs during the off period. The optimized duty cycle maintains proper voltage levels despite temperature-induced leakage.
Solution Approach 2:
The patent implements a duty cycle design that provides a cushion margin against leakage current effects. By ensuring the high-level duration is sufficiently long to account for expected leakage during the low-level period, the circuit preemptively compensates for temperature-related leakage issues before they can cause waveform abnormalities.
3Reliability
If clock signal duty cycle is optimized, then high temperature stability is improved, but RC delay may affect charging speed
Solution Approach 1:
The patent optimizes the duty cycle parameter to achieve a balance between stability and speed. The high-level duration is set long enough to ensure complete charging that overcomes leakage effects, while the overall period is kept sufficiently short to maintain acceptable charging speed. This parameter optimization resolves the contradiction between stability and speed by finding the optimal duty cycle value.
Solution Approach 2:
The patent employs dynamic duty cycle adjustment based on operating conditions. The duty cycle can be adapted to different temperature conditions and load requirements, allowing the circuit to maintain optimal performance across varying operating scenarios. This dynamic approach enables the system to prioritize stability when needed and speed when conditions permit.
Data Source
AI summary
The present invention relates to a GOA circuit for tablet display and a display device. The GOA circuit comprises cascaded plurality of GOA units, the GOA unit comprises a pull-up control part 400 and a transfer part 500; the transfer part 500 comprises a first thin film transistor T22, the gate thereof is connected with the gate signal point Q(n), the drain and the source are respectively input the clock signal CK(n) and output the turn-on signal ST(n); the pull-up control part comprises: a second thin film transistor T11, the gate thereof is input the turn-on signal ST(n−2), the drain and the source are respectively connected with the horizontal scan line G(n−2) and the gate signal point Q(n); a third tin film transistor T12, the gate thereof is connected with the horizontal scan line G(n−1), the drain and the source are respectively connected with the horizontal scan line G(n−1) and the gate signal point Q(n). The present invention also provides a related display device. The present invention can improve the stability of the GOA circuit and the related display device in high temperature.