GOA Circuit Topology for Pull-Up Node Leakage Reduction
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Solution Overview
Problem
Existing GOA circuits suffer from significant leakage current at the pull-up node, affecting the output waveform and preventing it from achieving a high enough peak value.
Innovation Solution
A GOA circuit design with reduced leakage-current paths, incorporating a pull-up module, inverter module, and pull-down module, utilizing specific thin-film transistor connections to minimize leakage current at the pull-up node.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple thin-film transistors are used on the leakage-current path of the pull-up node, then the circuit can perform pull-up and pull-down operations, but the leakage current at the pull-up node becomes serious
Solution Approach 1:
The circuit is divided into distinct functional modules: a pull-up module with first and second thin-film transistors, a pull-down module with fourth and fifth thin-film transistors, and an output module with third and sixth thin-film transistors. This segmentation isolates the leakage current paths to specific modules, preventing cumulative leakage effects across the entire circuit and enabling independent optimization of each module's transistor count.
Solution Approach 2:
The patent extracts and eliminates unnecessary thin-film transistors from the leakage current path of the pull-up node. By carefully designing the connection topology where only essential transistors remain on the critical path, the number of leakage sources is reduced while preserving the core pull-up and pull-down functionality.
2Area of stationary object
If thin-film transistors are placed on the leakage-current path, then the circuit can be compact, but the leakage current affects the output waveform peak value
Solution Approach 1:
Different regions of the circuit are assigned different transistor densities based on functional requirements. The output module and control modules use fewer transistors to minimize local leakage, while other regions maintain adequate transistor coverage for signal processing. This localized optimization ensures that critical output nodes maintain high signal integrity with minimal leakage interference.
Data Source
AI summary
The present disclosure relates to a GOA circuit and a display panel. The GOA circuit includes a plurality of cascaded GOA units, wherein each GOA unit includes a pull-up module, an inverter module, a pull-down module, and an output module. The pull-up module includes a first thin-film transistor and a second thin-film transistor. The first thin-film transistor is connected to a pull-up signal. The second thin-film transistor is connected to a pull-down node. The inverter module includes a seventh thin-film transistor. The seventh thin-film transistor is connected to a pull-up node. The pull-down module includes an eighth thin-film transistor and a ninth thin-film transistor. The eighth thin-film transistor and the ninth thin-film transistor are respectively connected to the pull-down node. In the output module, the gate of each thin-film transistor is connected to the pull-up node.