GOA Circuit Design for Narrow Frame Displays
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Solution Overview
Problem
The Gate Driver on Array (GOA) circuit in display panels occupies space, making it difficult to achieve a narrow frame size, and requires two pull-down units to maintain low-level scan lines, which complicates the design and increases the size of the circuit.
Innovation Solution
A driving circuit with a switching unit, clamping unit, pull-up unit, and pull-up control unit is implemented, using a second clock signal to prevent reverse current leakage and alternate the operation of switching units, reducing the need for multiple pull-down units and simplifying the design by using only one low-level control signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two pull-down units are used to maintain low-level scan lines, then the stability of the GOA circuit is improved, but the device complexity and size increase
Solution Approach 1:
The patent merges the functions of multiple pull-down units into a single pull-down unit that can selectively discharge different scan lines. This consolidation reduces the number of components while maintaining the ability to keep multiple scan lines at low levels, thereby reducing device complexity without sacrificing stability.
Solution Approach 2:
The patent introduces a dynamic control mechanism where the single pull-down unit can be selectively activated for different scan lines based on timing signals. This dynamic operation allows the simplified circuit to perform the same function as multiple static pull-down units would, maintaining circuit stability with fewer components.
2Area of stationary object
If the GOA circuit occupies space on the display panel, then the frame size increases, but the manufacturing yield decreases
Solution Approach 1:
By merging multiple pull-down units into one, the patent significantly reduces the area occupied by the GOA circuit. This space reduction allows the circuit to fit within narrower frame constraints while maintaining functionality, thereby improving manufacturing yield without compromising performance.
Solution Approach 2:
The patent optimizes the spatial arrangement of the GOA circuit by utilizing vertical stacking and compact routing techniques. This dimensional optimization allows the reduced circuit to be positioned in optimal locations on the display panel, maximizing yield while minimizing frame space occupation.
3Device complexity
If a single pull-down unit is used to maintain low-level scan lines, then the device complexity is reduced, but reverse current leakage occurs
Solution Approach 1:
The patent incorporates a clamp unit that performs preliminary action to prevent reverse current leakage before it can affect the circuit. The clamp unit actively monitors and corrects voltage levels, ensuring that when the single pull-down unit operates, reverse current leakage is blocked in advance, maintaining circuit integrity with simplified design.
Solution Approach 2:
The clamp unit serves as an intermediary component between the single pull-down unit and the scan lines. It mediates the potential harmful effect of reverse current leakage by providing a controlled path that prevents current from flowing backward, thereby allowing the simplified single-unit design to operate without generating harmful leakage currents.
Data Source
AI summary
A driving circuit of a display panel includes a switching unit, a clamping unit that prevents reverse current leakage, a reference signal line coupled to a low level signal, a pull-up unit, and a pull-up control unit that drives the pull-up unit. An input end of the pull-up unit receives a second clock signal, and an output end of the pull-up unit is coupled to a current scan line, where the current scan line is coupled to a pull-down maintain unit, and the pull-down maintain unit includes a first switching unit and a second switching unit. The first switching unit and the second switching unit are connected between the current scan line and the reference signal line in parallel, where a control end of the first switching unit and a control end of the second switching unit are coupled to an output end of the switching unit, a control end of the switching unit receives a first clock signal, and an input end of the switching unit receives the second clock signal through the clamping unit.