Gate Driver on Array Circuit for Narrow Frame LCD
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Solution Overview
Problem
The existing gate driver on array (GOA) circuits occupy large circuit design space, making it difficult to meet the ultra-narrow frame requirements of liquid crystal display panels due to the large number of units and complex design needed.
Innovation Solution
The proposed solution involves a GOA circuit design where three stages of scan driving signals are outputted through one gate driver on array unit, reducing the average frame space occupied by each stage, achieved through a cascade-coupled configuration with pull-up, pull-down, and holding circuits using thin film transistors, and specific signal control mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the existing GOA circuit design with multiple units is used, then the scanning function is achieved, but the circuit design space occupied is large
Solution Approach 1:
The patent merges the functions of multiple GOA units into a single integrated unit. The gate driver on array unit is designed to output scan driving signals for multiple stages (n, n+1, n+2) simultaneously, combining what would traditionally require separate units into one compact circuit structure, thereby reducing the overall circuit design space.
Solution Approach 2:
The gate driver on array unit is designed with multi-functionality to serve multiple stages. A single unit can drive three different stages of the display panel, making it a universal component that replaces multiple specialized units, thus reducing both the number of components and the total area occupied.
2Adaptability or versatility
If more GOA units are used to cover more stages, then the scanning coverage is improved, but the frame space occupied increases
Solution Approach 1:
The patent combines the scanning functionality for multiple stages into a single frame space. By designing one GOA unit to handle three stages, the frame space required is reduced to approximately one-third of what would be needed if separate units were used for each stage.
Solution Approach 2:
The patent transitions from a one-to-one mapping (one unit per stage) to a one-to-many mapping (one unit for multiple stages). This dimensional change in the relationship between units and stages allows multiple scanning functions to coexist within a single frame space allocation.
Data Source
AI summary
Disclosed is a GOA circuit, including GOA units, which are cascade coupled. An nth stage GOA unit charges nth stage, n+1th stage and n+2th stage horizontal scanning lines. The nth stage GOA unit includes a pull-up control circuit, receiving a start signal CT and outputting a pull-up control signal Q(n); a pull-up circuit, receiving Q(n), an nth stage clock signal CK(n), an n+1th stage clock signal CK(n+1) and an n+2th stage clock signal CK(n+2), and outputting an nth stage transfer signal ST(n), an nth stage scan driving signal G(n), an n+1th stage scan driving signal G(n+1) and an n+2th stage scan driving signal G(n+2); a pull-down circuit, receiving an n+6th stage scan driving signal G(n+6) and a first direct current low voltage signal VSSQ1 to enable Q(n) in an off state. Three stages scan driving signals can be outputted through one stage GOA unit.