GOA Circuit TFT Aging Reduction via Periodic Pull-Down Control
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Solution Overview
Problem
The aging of thin-film transistors (TFTs) in gate driver on array (GOA) circuits for liquid crystal displays (LCDs) is accelerated due to prolonged conducted time and high power consumption, which affects the reliability and efficiency of the LCDs.
Innovation Solution
The GOA circuit design includes additional TFTs in the pull-down maintaining circuit, with their gates receiving a clock signal and drains receiving a square-wave signal, reducing the conducted time and incorporating a beveled control signal circuit to manage clock signals and scanning voltages, thereby controlling the TFTs' operation and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the pull-down maintaining circuit operates continuously to maintain low voltage level, then the scanning signal can be properly maintained, but the TFTs age rapidly and power consumption increases
Solution Approach 1:
The patent applies periodic action by controlling the pull-down maintaining circuit to operate only during specific time periods (when scanning signals need to be maintained at low level) rather than continuously. The circuit is activated by clock signals and control signals that enable it to function periodically, reducing the cumulative conducted time of TFTs while maintaining scanning signal integrity when needed.
Solution Approach 2:
The patent implements dynamics by making the pull-down maintaining circuit dynamically controllable through additional control signals and clock inputs. The circuit can be selectively enabled or disabled based on operational requirements, allowing the system to adapt the TFT conducted time according to actual scanning needs, thereby balancing reliability with component lifespan.
2Reliability
If the pull-down maintaining circuit operates continuously, then the scanning signal low level is maintained, but power consumption increases
Solution Approach 1:
The pull-down maintaining circuit is designed to operate periodically rather than continuously, being activated only when scanning signals require low level maintenance. This periodic operation significantly reduces power consumption while maintaining signal stability during critical periods.
Solution Approach 2:
The patent applies partial action by providing multiple pull-down maintaining circuits (first and second) that can be selectively activated. Not all circuits need to operate simultaneously or continuously, allowing the system to use only the necessary portion of the maintaining circuitry, thereby reducing overall power consumption while ensuring scanning signal stability when needed.
Data Source
AI summary
A gate driver on array (GOA) circuit includes cascaded GOA unit circuits. An nth stage GOA unit circuit includes a clock signal source, a constant voltage supply, a pull-up control circuit, a pull-up circuit, a downlink circuit, a pull-down circuit, a pull-down maintaining circuit, a bootstrap capacitor and a conducting control circuit. An output terminal of the pull-up control circuit is electrically connected to the pull-up circuit, the downlink circuit, the pull-down circuit, the pull-down maintaining circuit, and the bootstrap capacitor. The constant voltage supply is electrically connected to the pull-down maintaining circuit and the pull-down circuit. The clock signal source is electrically connected to the pull-up circuit, the downlink circuit, and the conducting control circuit. The conducting control circuit is electrically connected to the pull-down maintaining circuit.