GOA Circuit Voltage Stability and Ripple Reduction
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Solution Overview
Problem
The conventional gate driver on array (GOA) circuit for liquid crystal displays experiences delays in gate signal output due to voltage level imbalances and increased ripple current, leading to potential circuit failure and reduced reliability.
Innovation Solution
The proposed GOA circuit incorporates additional TFTs and a bridge circuit to alternate clock signal frequencies, compensating voltage imbalances and reducing TFT sizes, thereby improving pull-down voltages and minimizing ripple current across nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional GOA circuit uses standard pull-down holding circuit configuration, then circuit structure is simple, but gate signal output delay occurs and reliability decreases
Solution Approach 1:
The pull-down holding circuit is divided into two separate circuits: a first pull-down holding circuit connected to the gate signal node and a second pull-down holding circuit connected to the output node. This segmentation allows independent optimization of each circuit's function, reducing signal delay while maintaining structural clarity.
Solution Approach 2:
A bridge circuit is introduced as an intermediary component connecting the first and second pull-down holding circuits. This bridge circuit mediates the interaction between the two circuits, enabling coordinated voltage control and improving overall circuit reliability without excessive complexity.
2Stability of the object's composition
If additional TFTs are added to compensate voltage imbalances, then voltage stability improves, but device complexity increases
Solution Approach 1:
Different TFTs are configured with different characteristics to address local voltage imbalances. The first TFT in the first pull-down holding circuit and the second TFT in the second pull-down holding circuit are optimized for their specific locations, providing targeted voltage compensation rather than uniform adjustments throughout the circuit.
Solution Approach 2:
The circuit employs dynamic voltage compensation where the bridge circuit actively adjusts voltage levels based on real-time conditions. This dynamic approach maintains voltage stability without requiring a fixed increase in TFT数量, as the system adapts to changing operational states.
3Speed
If clock signal frequencies are increased to reduce delay, then gate signal output speed improves, but ripple current increases causing potential circuit failure
Solution Approach 1:
The circuit uses periodic clock signals with optimized frequency characteristics to drive the pull-down holding circuits. By carefully selecting the periodic frequency and duty cycle, the circuit achieves fast gate signal output while the periodic nature helps cancel out ripple current through constructive and destructive interference patterns.
Solution Approach 2:
The bridge circuit is designed to convert the potentially harmful ripple current into a beneficial effect. By strategically positioning the bridge circuit and adjusting its parameters, the ripple current generated by high-frequency clock signals is transformed into useful voltage compensation that further stabilizes the gate signal output.
Data Source
AI summary
A gate driver on array (GOA) circuit for an LCD includes multiple cascaded GOA units. A Nth stage GOA unit controls a charging of a Nth stage horizontal scanning line. The Nth stage GOA unit includes a pull-up circuit, a pull-down circuit, a first pull-down holding circuit, a second pull-down holding circuit, a bridge circuit, a pull-up control circuit, a transfer circuit, and a boast capacitor. A seventh TFT connects in parallel with a third TFT of the first pull-down holding circuit. A fourteenth TFT connects in parallel with a tenth TFT of the second pull-down holding circuit. The gate of the seventh TFT and the gate of the fourteenth TFT are connected, and both connected to a starting signal from (N−1)th GOA unit or a (N−1)th stage horizontal scanning line. An LCD device also uses the GOA circuit to reduce the delay of the gate signal output.