Gate on Array Circuit Non-Symmetrical Waveform Design
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Solution Overview
Problem
Conventional Gate on Array (GOA) circuits have long falling times for scan signals, which hinder the timely switching of TFTs in pixel circuits, leading to incomplete charging of data due to extended voltage storage requirements, particularly in high-resolution displays.
Innovation Solution
A GOA circuit design featuring cascaded stages with pull-up control, hand-down, feedback, pull-up, bootstrap capacitor, and pull-down units, including transistors and capacitors, to generate non-symmetrical waveforms that reduce the decline time of scan signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional GOA circuits are used, then the circuit structure is simple, but the falling time of scan signals is too long
Solution Approach 1:
The GOA circuit is divided into multiple functional units including pull-up control units, hand-down units, feedback units, pull-up units, bootstrap capacitor units, pull-down units, and pull-down control units. Each unit performs a specific function in generating and controlling the scan signal waveform, allowing the complex task of waveform generation to be segmented into manageable components that work together to achieve the desired fast falling time.
Solution Approach 2:
The circuit generates non-symmetrical waveforms where the rising edge and falling edge have different characteristics. The pull-up portion and pull-down portion are controlled separately with different timing and voltage levels, creating an asymmetric waveform that optimizes the falling time while maintaining adequate rising time for proper TFT switching.
2Productivity
If the falling time is reduced for high-resolution displays, then the charging performance improves, but the circuit complexity increases
Solution Approach 1:
Feedback units are incorporated to monitor the voltage levels and signal transitions, automatically adjusting the waveform generation to maintain optimal charging performance. The feedback mechanism ensures that the scan signal maintains appropriate voltage levels and timing characteristics regardless of variations in the display panel characteristics or operating conditions.
Solution Approach 2:
The circuit performs preliminary charging of the storage capacitor before the actual data writing phase. The pull-up control units prepare the voltage levels in advance, and the bootstrap capacitors are pre-charged to ensure that when the scanning begins, the TFTs can be switched on quickly and the data can be written without delay, effectively reducing the overall charging time.
Data Source
AI summary
The present disclosure provides a gate on array (GOA) circuit. Each stages of GOA units of the GOA circuit includes a pull-up control unit, a hand-down unit, a feedback unit, a first pull-up unit, a second pull-up unit, a bootstrap capacitor unit, a pull-down unit, and a pull-down control unit. The bootstrap capacitor and the second pull-up unit of the GOA circuit make the first node have a non-symmetrical waveform. The right part of the waveform is as high as the highest voltage potential of the first node so that the decline time of the scan signal is reduced and the performance of the GOA circuit is improved.