GOA Clock Lead Layout for Uniform LCD Timing and Mura Prevention
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Solution Overview
Problem
In Gate On Array (GOA) driving designs for LCDs, varying lengths of clock signal leads cause different coupling capacitances with the Black Matrix layer, leading to signal delays and horizontal Mura defects, which are difficult to address without additional capacitance compensation regions, hindering the design of ultra-narrow bezels.
Innovation Solution
The display substrate features clock signal leads of equal length extending from one clock signal line to another, ensuring all clock signal lines have the same length, which compensates for coupling capacitances and prevents horizontal Mura without the need for additional capacitance compensation regions, facilitating an ultra-narrow bezel design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If different clock signal leads are used to couple CLK lines to TFT regions in GOA driving architecture, then clock signals can be provided to different positions, but different lead lengths cause different coupling capacitances with the Black Matrix layer, resulting in signal delay differences and horizontal Mura defects
Solution Approach 1:
The patent changes the geometric parameter of clock signal leads by configuring them to extend in the same direction (first direction) with equal lengths in the first direction. This parameter standardization ensures that all clock signal leads have identical coupling capacitances with the Black Matrix layer, thereby eliminating signal delay differences and horizontal Mura defects while maintaining effective clock signal distribution across different TFT regions
2Manufacturing precision
If capacitance compensation regions are added to compensate for coupling capacitance differences, then signal timing uniformity can be improved, but the bezel size increases and ultra-narrow bezel design is hindered
Solution Approach 1:
The patent extracts and eliminates the need for separate capacitance compensation regions by directly addressing the root cause through lead configuration. By making all clock signal leads extend in the same direction with equal lengths, the design inherently achieves uniform coupling capacitances without requiring additional compensation structures, thus maintaining ultra-narrow bezel dimensions while ensuring signal timing uniformity
Data Source
AI summary
The present disclosure provides a display substrate and a display device. The display substrate includes: a gate driving circuitry arranged at a peripheral region of the display substrate; n clock signal leads coupled to the gate driving circuitry, each clock signal lead extending in a first direction; and n clock signal lines arranged sequentially in the first direction, each clock signal line extending in a second direction intersecting the first direction, where n is a positive integer greater than 1. The clock signal leads have a same length in the first direction, each clock signal lead extends from a first clock signal line to an nth clock signal line, and each clock signal lead is coupled to a corresponding clock signal line at a position where the clock signal lead intersects the clock signal line.