GOA Circuit Clock Signal Load Balancing for 8K Display Uniformity
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Solution Overview
Problem
Current 8K display panels experience periodic dark lines at low gray levels due to uneven loading of clock signal lines, which affects the display effect.
Innovation Solution
A display panel design featuring a gate driver on array (GOA) circuit with cascaded GOA units, including both effective and redundant units, where each clock signal line is connected to an equal number of units, ensuring uniform load distribution and eliminating periodic dark lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the number of GOA units connected to each clock signal line is not uniform, then the device complexity is reduced, but periodic dark lines are generated at low gray levels affecting display effect
Solution Approach 1:
The patent applies local quality by introducing redundant GOA units specifically at positions where clock signal lines would otherwise have uneven loads. Instead of uniformly distributing all GOA units, the design selectively places additional units connected to certain clock signal lines to balance the load distribution locally, thereby eliminating periodic dark lines while maintaining overall system functionality.
2Illumination intensity
If redundant GOA units are added to balance clock signal line loads, then display uniformity is improved, but device complexity increases
Solution Approach 1:
The patent uses the copying principle by creating redundant GOA units that are identical copies of the standard GOA unit structure. These copied units are strategically placed and connected to clock signal lines to balance loads without requiring new or modified unit designs, thus achieving display uniformity improvement while limiting the increase in device complexity to merely additional unit instances rather than structural complexity.
Data Source
AI summary
The present invention provides a display panel and an electronic device. A gate driver on array (GOA) circuit in the display panel includes a plurality of cascaded GOA units. The GOA units include a plurality of effective GOA units and 2m redundant GOA units arranged in sequence. The plurality of effective GOA units forms a plurality of effective GOA modules that are arranged in sequence. In the effective GOA module, the 2m effective GOA units are sequentially connected to the 2m clock signal lines, and the 2m redundant GOA units are sequentially connected to the 2m clock signal lines. The display panel of the present invention has no periodic dark lines at low gray levels.