GOA Control Circuit Signal Line Reduction
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Solution Overview
Problem
Existing display apparatus architectures with a one-to-one relationship between timing controller output signals and scanning management signals result in a large number of signal lines, leading to high costs and design complexity, especially in high-resolution applications, and are not adaptable to display panels with varying parameters.
Innovation Solution
A display apparatus comprising a timing control circuit and a gate-driver on array (GOA) control circuit, which includes a scanning signal management circuit that generates scanning control signals based on frame synchronization, predetermined panel parameters, and an operation clock signal, reducing the number of signal lines required between the timing control circuit and the GOA control circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a one-to-one relationship between timing controller output signals and scanning management signals is used, then the control precision is improved, but the number of signal lines increases enormously
Solution Approach 1:
The timing controller is designed to generate multiple scanning management signals (CLK, VST, VRST, etc.) through a small number of output signal lines. Instead of requiring one dedicated signal line for each control function, the timing controller uses universal signal lines that can generate different scanning management signals based on control signals received from the GOA control circuit, thereby reducing the total number of signal lines while maintaining precise control over the display panel units.
Solution Approach 2:
The GOA control circuit acts as an intermediary between the timing controller and the display panel units. It receives control signals from the timing controller and generates the corresponding scanning management signals locally. This intermediary approach allows the timing controller to use fewer signal lines while still achieving precise control, as the GOA control circuit translates the control signals into the specific scanning management signals needed for each display panel unit.
2Measurement precision
If dedicated architecture for single display panel model is used, then the control precision for that model is improved, but the adaptability to different panel models deteriorates
Solution Approach 1:
The system employs dynamic configuration where the timing controller and GOA control circuit can adapt their operation based on the specific display panel model being used. The GOA control circuit receives control signals and generates scanning management signals that are tailored to the specific panel parameters, allowing the system to maintain high control precision for each model while being adaptable to multiple different models through programmable control logic.
Solution Approach 2:
The system allows for parameter changes to accommodate different display panel models. The GOA control circuit can be configured with different panel parameters (such as resolution, scanning frequency, timing characteristics) through control signals from the timing controller. This enables the same hardware architecture to achieve precise control for various panel models by dynamically adjusting the control parameters rather than requiring dedicated hardware for each model.
3Ease of operation
If numerous signal lines are used between timing controller and level shifter, then the control capability is improved, but the device complexity and cost increase
Solution Approach 1:
The GOA control circuit combines multiple control functions into a single integrated circuit that can generate various scanning management signals (CLK, VST, VRST, etc.) from a limited set of control signals received from the timing controller. This merging of functions reduces the number of separate signal lines and components needed, thereby reducing device complexity and cost while maintaining comprehensive control capability over the display panel units.
Data Source
AI summary
A display apparatus includes a timing controller and a gate-driver on array (GOA) control circuit. The timing controller generates a frame synchronization signal. The GOA control circuit is coupled to the timing controller and includes a scan signal management circuit and a level shifter. The scan signal management circuit generates a scan signal management signal according to the frame synchronization signal, a predetermined panel parameter, and an operation clock signal. The scan signal management circuit includes a storage unit which stores the predetermined panel parameter. The level shifter generates a scan control signal according to the scan signal management signal to control a GOA of a display panel circuit. The GOA generates a gate driving signal to control a vertical scan operation of the display panel circuit.