GOA Display Driving Circuit With Asymmetric Clock Timing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing display products face challenges in achieving narrow frames, high resolution, and high refresh rates due to the limitations of bilaterally symmetrical Gate On Array (GOA) design, which restricts wiring space and makes it difficult to meet product requirements.
Innovation Solution
A display driving circuit with two gate driving circuits on opposite sides of the display panel, sharing a pull-up node and overlapping clock signal potentials to enhance driving signal capabilities, reducing the number of transistors needed for controlling potential nodes, and incorporating capacitors to manage signal transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If bilaterally symmetrical Gate On Array (GOA) model design is used, then device complexity is reduced, but wiring space is restricted and it is difficult to achieve narrow frame and high resolution
Solution Approach 1:
The patent employs asymmetric clock signal timing for different gate lines. Specifically, odd-numbered gate lines use a first clock signal with a first valid level duration, while even-numbered gate lines use a second clock signal with a second valid level duration. This asymmetric design allows optimization of signal transmission timing for different regions, improving overall display performance while enabling narrower frames and higher resolution without increasing device complexity
2Ease of manufacture
If bilaterally symmetrical GOA design is used, then manufacturing is simplified, but it is difficult to meet high refresh rate requirements
Solution Approach 1:
The patent implements dynamic clock signal timing where the valid level duration of clock signals varies depending on the gate line number. Odd-numbered gate lines receive clock signals with one duration, while even-numbered gate lines receive clock signals with another duration. This dynamic timing adjustment optimizes the refresh rate for different regions of the display panel, enabling high refresh rates while maintaining ease of manufacture through a unified circuit architecture
3Device complexity
If clock signal valid level durations are made equal, then circuit design is simplified, but driving ability of gate lines becomes unbalanced
Solution Approach 1:
The patent applies local quality optimization by assigning different clock signal valid level durations to different gate lines based on their specific requirements. Odd-numbered gate lines use a first clock signal duration, while even-numbered gate lines use a second clock signal duration. This localized timing adjustment ensures balanced driving ability across all gate lines, improving display uniformity and reliability while keeping the overall circuit design manageable
Data Source
AI summary
The present disclosure provides a display driving circuit and a display device. The display driving circuit includes two gate driving circuits, the gate driving circuit includes a plurality of cascaded driving circuits; the driving circuit includes N clock signal terminals, N output sub-circuits and N driving signal output terminals; N is an integer greater than or equal to 2; the N output sub-circuits share a first pull-up node; an ith driving signal output terminal of one driving circuit is electrically connected to an (i+j)th driving signal output terminal of the other driving circuit, and both i and j are positive integers, i is a positive integer less than or equal to N, j is a positive integer less than or equal to N, and i+j is a positive integer less than or equal to N.