GOA Display Panel Narrow Bezel Design
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing GOA display panels face challenges in achieving a narrow bezel design for large-size and high-resolution displays due to increased RC loading, which results in a wider bezel area that fails to meet consumer demands and lacks market competitiveness.
Innovation Solution
The GOA display panel design rearranges the cascaded GOA unit group from the bezel area to the display area, with a trace group in the bezel area electrically connected to the GOA unit group, featuring a GOA bus and common electrode line, allowing for a super narrow bezel by minimizing the width of the trace group to less than or equal to 1.2 micrometers, thus avoiding data line overlap and ensuring uniform RC loading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If the GOA circuit is disposed in the bezel area, then the driving circuit function is achieved, but the bezel width increases and cannot meet narrow bezel design requirements
Solution Approach 1:
The patent segments the GOA circuit into two functional parts: the GOA unit group (gate driver units) is placed in the display area, while the trace group (signal transmission lines) remains in the bezel area. This segmentation allows the bezel width to be reduced while maintaining driving circuit functionality through the distributed architecture.
Solution Approach 2:
The patent transitions from a traditional planar bezel-based layout to a spatial distribution across two dimensions: the display area (for GOA units) and the bezel area (for trace groups). This dimensional redistribution enables narrow bezel design by utilizing the display area for circuit functions previously confined to the bezel.
2Reliability
If the GOA bus width is increased to reduce RC loading, then signal transmission quality improves, but the bezel area width increases
Solution Approach 1:
The patent segments the signal transmission path into multiple trace groups distributed across the bezel area, each serving specific GOA units in the display area. This segmentation allows for optimized trace routing that reduces RC loading without requiring excessive bus width in any single location, thereby maintaining narrow bezel dimensions.
3Measurement precision
If the pixel size is reduced to increase resolution, then display quality improves, but the space between GOA layouts increases making narrow bezel design difficult
Solution Approach 1:
The patent redistributes GOA units across the display area in a manner that accommodates high-resolution pixel arrangements. By placing GOA units within the display area rather than confining them to the bezel, the design achieves high resolution with adequate spacing for GOA layouts without compromising bezel narrowness.
Data Source
AI summary
A gate driver on array (GOA) display panel is provided, including a display area, a bezel area, a plurality of pixel units, and a GOA circuit. The plurality of pixel units are disposed in the display area in an array. The GOA circuit includes a GOA unit group and a trace group. The GOA unit group is disposed in the display area. The trace group is electrically connected to the GOA unit group and is disposed in the bezel area. The trace group includes a GOA bus and a common electrode line. A super narrow bezel design is achieved by arranging the cascaded GOA unit group of the GOA circuit within the display area.