GOA Display Substrate Gate Scan Line Grouping for Narrow Bezel
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional gate driving circuit architectures in display technologies result in a large bezel area, hindering the achievement of ultra-narrow bezel displays due to the need for extensive space for shift registers and thin film transistors, which affects the screen-to-body ratio and display effectiveness.
Innovation Solution
The display substrate employs a gate driving circuit on array (GOA) technology, where gate scan signal lines are grouped and connected to multiple rows of sub-pixels, reducing the number of shift registers and gate scan signal lines required, allowing for a more compact design by synchronously controlling n rows of sub-pixels with each group of gate scan signal lines, thereby minimizing the bezel area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional gate driving circuit architecture is used with separate gate scan signal lines for each row of sub-pixels, then each row can be controlled independently, but the number of gate scan signal lines and shift registers increases, resulting in larger bezel area
Solution Approach 1:
The patent merges the control of multiple rows of sub-pixels into a single gate scan signal line. Specifically, one gate scan signal line is electrically connected to control switches in multiple rows of sub-pixels simultaneously, allowing these rows to be controlled in a time-division multiplexed manner. This merging reduces the total number of gate scan signal lines and shift registers required, thereby decreasing the bezel area occupied by the gate driving circuit.
Solution Approach 2:
The patent implements periodic action through time-division multiplexing, where a single gate scan signal line sequentially controls different rows of sub-pixels at different time intervals within each frame period. The control switches in different rows are activated in sequence, allowing one signal line to serve multiple rows periodically, thus reducing the overall complexity and bezel area.
2Device complexity
If gate scan signal lines are grouped to control multiple rows of sub-pixels, then the number of shift registers is reduced, but it requires careful design to maintain uniform connection distances and minimize signal loss
Solution Approach 1:
The patent applies local quality by strategically positioning control switches within each sub-pixel and designing the gate scan signal line routing to maintain relatively uniform connection distances to the control switches of different rows. This local optimization ensures that signal transmission quality remains consistent across all rows controlled by a single gate scan signal line, minimizing signal loss and maintaining reliability.
3Measurement precision
If more gate scan signal lines are used to control each row independently, then control precision is higher, but the bezel area increases, affecting screen-to-body ratio
Solution Approach 1:
The patent uses periodic action through time-division multiplexing to achieve both reduced bezel area and maintained control precision. Each row of sub-pixels is controlled in sequential time slots by the shared gate scan signal line, ensuring that each row receives precise control signals at the appropriate time, while the overall number of signal lines is reduced to minimize bezel area.
Solution Approach 2:
The gate scan signal line is designed with multi-functionality, serving multiple rows of sub-pixels that would traditionally require separate dedicated lines. This universal approach allows a single signal line to perform the control function for multiple rows, reducing the total number of lines needed and thereby decreasing bezel area while maintaining control precision through time-division multiplexing.
Data Source
AI summary
A display substrate has a display area and a peripheral area. The display substrate includes a plurality of sub-pixels, a plurality of groups of gate scan signal lines, and a plurality of groups of data lines. Each group of gate scan signal lines includes at least one gate scan signal line, each group of data lines includes n data lines, and the plurality of sub-pixels are arranged in an array; and n is greater than or equal to 2. A group of gate scan signal lines is electrically connected to n rows of sub-pixels. A column of sub-pixels is electrically connected to a group of data lines, and includes a plurality of groups of sub-pixels. Each group of sub-pixels includes n sub-pixels. The n sub-pixels are respectively electrically connected to n data lines in the group of data lines to which this column of sub-pixels is electrically connected.