GOA Driver Module With Dual-Terminal Gate-Line Discharge
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Solution Overview
Problem
Single-sided Gate On Array (GOA) drive in display technologies leads to large signal delay at the far terminal of a gate line, causing poor display due to far-terminal signal overcharging and pixel voltage differences, especially in the falling edge of the gate pulse signal.
Innovation Solution
A driver module with a control unit and control circuits, including control transistors, is designed to simultaneously control both the far and near terminals of the gate lines to receive ineffective voltage signals when the drive signal changes, reducing signal delay and ensuring simultaneous signal drop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If single-sided GOA drive is adopted, then device complexity is reduced and ease of manufacture is improved, but signal delay at far terminal increases causing poor display quality
Solution Approach 1:
The gate line control is segmented into two independent control systems: a first control circuit controlling the first terminal and a second control circuit controlling the second terminal. This segmentation allows each terminal to be controlled independently, resolving the signal delay issue in single-sided drive while maintaining manufacturing simplicity.
Solution Approach 2:
Different control strategies are applied to different terminals of the gate line. The first control circuit applies a first control signal to the first terminal, while the second control circuit applies a second control signal to the second terminal. This local differentiation optimizes signal delivery quality at each terminal without requiring complete redesign of the entire drive system.
2Device complexity
If single-sided GOA drive is used, then device structure is simplified, but signal delay causes far-terminal signal overcharging and pixel voltage differences
Solution Approach 1:
The control system is divided into two independent control circuits, each responsible for one terminal of the gate line. This segmentation enables precise timing control at each terminal without requiring complex coordinated control, maintaining relatively simple device structure while improving signal timing precision.
Solution Approach 2:
The control circuits are designed to proactively manage signal delivery by applying control signals that anticipate and prevent signal delay issues. The first and second control circuits generate control signals that ensure simultaneous arrival of effective signals at both terminals, preventing far-terminal signal overcharging before it occurs.
3Device complexity
If single-sided GOA drive is implemented, then driver IC requirements are reduced, but falling edge delay of gate pulse signal increases
Solution Approach 1:
The drive function is segmented between two control circuits operating on opposite sides of the gate line. Each control circuit handles the timing for its respective terminal, which eliminates the cumulative delay issue in single-sided drive where the signal must traverse the entire gate line length from one end.
Solution Approach 2:
The control circuits are designed to generate control signals in advance that compensate for signal propagation delays. By preparing and applying control signals that account for the expected delay, the system ensures that effective signals arrive at both terminals simultaneously, reducing the practical impact of signal delay without requiring complex driver ICs.
Data Source
AI summary
A driver module includes a first driver unit and a first control unit; the first driver unit includes M levels of first driver circuits; M is a positive integer; m is a positive integer less than or equal to M; the m-th level first drive signal output terminal is electrically connected to a first terminal of an m-th row first gate line, to provide an m-th level first drive signal to the m-th row first gate line; the first control unit includes M first control circuits; an m-th first control circuit included in the first control unit is electrically connected to a second terminal of the m-th row first gate line, configured to control the second terminal of the m-th row first gate line to receive an ineffective voltage signal when a voltage value of the m-th level first drive signal changes from an effective voltage to an ineffective voltage.