GOA Circuit Stability via Dual Clock Driving
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Solution Overview
Problem
Current Gate-On-Array (GOA) CMOS circuits in liquid crystal display technology face issues with stability and high power consumption due to their design, particularly affecting the border width and reliability of display devices.
Innovation Solution
The implementation of a GOA circuit with multiple cascaded units, each comprising a transferring circuit, a latch circuit, and an output circuit, utilizing two clock signals for simultaneous driving to enhance stability and reduce power consumption by optimizing the voltage level transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional single clock signal driving is used in GOA circuit, then the circuit structure is simple, but the circuit stability is poor and failures occur during voltage level changes
Solution Approach 1:
The patent combines two clock signals (first clock signal and second clock signal) to drive the same GOA circuit simultaneously. The latch circuit receives both clock signals and uses them together to control the transfer of stage transfer signals, thereby improving circuit stability during voltage level transitions while maintaining a unified circuit architecture.
Solution Approach 2:
The patent introduces a reset signal that operates in conjunction with the two clock signals to preemptively prevent potential failures. The reset signal is designed to work with the clock signals to ensure stable voltage level transitions before failures can occur, providing a cushioning effect against potential circuit instabilities.
2Loss of energy
If conventional GOA CMOS circuit is used, then the manufacturing process is simple, but the power consumption is high
Solution Approach 1:
The patent employs periodic action by using two clock signals that operate in alternating phases. The latch circuit responds to the periodic transitions of both clock signals, enabling the GOA circuit to function with reduced power consumption through this periodic driving scheme while maintaining necessary circuit functionality.
Solution Approach 2:
The patent changes the operating parameters of the GOA circuit by introducing dual clock signals with different phases and utilizing a latch circuit that responds to these parameter changes. This parameter modification enables more efficient power utilization compared to conventional single clock signal driving.
3Length of moving object
If GOA circuit width is reduced for narrow frame design, then the display border is narrower, but the circuit stability deteriorates
Solution Approach 1:
The patent combines two clock signals to drive the compact GOA circuit, providing enhanced stability compensation for the reduced circuit width. This merging of clock signals ensures that even with a narrower GOA circuit designed for narrow frame displays, the circuit maintains adequate stability during operation.
Data Source
AI summary
A GOA circuit and an LCD device. The GOA circuit includes multiple cascaded GOA units, and each includes a transferring circuit, a latch circuit and an output circuit. In a forward scanning, the transferring circuit receives a (N−1)th stage-transfer signal of a (N−1)th stage, and sending to the latch circuit. In a backward scanning, the transferring circuit receives a (N+1)th stage-transfer signal of a (N+1)th stage, and sending to the latch circuit. In the canning period, the latch circuit receives a first clock signal and a second clock signal simultaneously, and outputs an Nth stage-transfer signal the same as the first clock signal and opposite to the second clock signal. The output circuit receives the Nth stage-transfer signal, and outputs an Nth scanning signal the same as the Nth stage-transfer signal. The present invention utilizes two clock signals to commonly drive the GOA circuit to improve the stability.