Array Substrate GOA Fan-Out Layout for Narrow Source Borders

The patent applies dimensionality change by routing GOA timing signal lines (CK lines) through the fan-out region in a different spatial arrangement. Instead of routing all signal lines through the border region from COF, the CK lines are introduced into the fan-out region and distributed to different data line groups, effectively utilizing the fan-out region's three-dimensional space to reduce border width while maintaining signal transmission functionality.

The patent segments the GOA timing signal distribution by dividing CK lines into multiple groups (first CK lines and second CK lines) that are separately routed to different data line groups. This segmentation allows independent optimization of signal paths, enabling the first CK lines to serve first data line groups and second CK lines to serve second data line groups, thereby reducing the overall border width requirement.

The patent applies local quality by positioning different types of GOA signal lines (CK lines, ELVDD lines, ELVSS lines) in specific local regions between adjacent source fan-out line groups. Each signal line type is routed through optimally positioned regions that balance border width reduction with signal transmission requirements, ensuring that critical signals maintain appropriate transmission characteristics while achieving narrow border design.

The patent uses the fan-out region as an intermediary zone between the GOA drive circuit and the data line groups. By positioning GOA signal lines between source fan-out line groups within this intermediary region, the design allows signal distribution to occur in a controlled manner that reduces border width while maintaining transmission efficiency through proper signal routing and spacing.