GOA Circuit Forced Pull-Down Unit for Clock Signal Failure
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional GOA circuits in LCD devices are prone to damage due to the sudden disappearance of clock signals, causing high current and potential damage to the device.
Innovation Solution
Incorporating a forced pull-down unit within the GOA circuit that forces the first node to a low level when clock signals are absent, utilizing additional TFTs and reset signals to manage the node's potential during signal interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the conventional GOA circuit operates without additional protection components, then the circuit complexity is low, but the reliability deteriorates when clock signals disappear
Solution Approach 1:
The patent applies preliminary anti-action by pre-configuring the forced pull-down unit with a reset signal that is normally low but automatically activates when clock signals disappear. This preemptive mechanism counteracts the potential harmful effect of clock signal failure before it can cause damage, by ensuring the first node is pulled down to low level as soon as the clock signal interruption is detected.
Solution Approach 2:
The patent implements beforehand cushioning by adding the forced pull-down unit as a protective buffer against clock signal failures. This additional component absorbs the shock of signal interruption by providing an alternative path to ground, preventing the high current surge that would otherwise damage the LCD device.
2Ease of operation
If the clock signal is used to control the pull-up unit, then the gate driving function is achieved, but high current damage occurs when the clock signal disappears
Solution Approach 1:
The patent introduces an intermediary mechanism - the forced pull-down unit - that acts as a mediator between the clock signal control and the pull-up unit. When the clock signal disappears, this intermediary component activates to pull down the first node, preventing the harmful high current from flowing through the pull-up unit and damaging the LCD device.
Solution Approach 2:
The patent implements feedback by using the clock signal status to control the reset signal that activates the forced pull-down unit. When the clock signal is present, the reset signal remains low and disables the pull-down unit. When the clock signal disappears, the reset signal automatically goes high, enabling the pull-down unit to counteract the potential damage.
Data Source
AI summary
A GOA driving circuit includes a plurality of cascaded GOA units and outputs a gate driving signal to an Nth-stage horizontal scanning line of a display region by an Nth-stage GOA unit. The Nth-stage GOA unit includes a pull-up unit, a pull-up control unit, a pull-down unit, a pull-down sustaining unit, a download unit, and a bootstrap capacitor unit. The pull-up unit, the pull-down unit, the pull-down sustaining unit, and the bootstrap capacitor unit are respectively electrically connected with a first node and an Nth-stage horizontal scanning line. The pull-up control unit and the download unit are electrically connected with the first node. N is a positive integer. The Nth-stage GOA unit further includes a forced pull-down unit, which is used to force the first node to low level when clock signals are disappeared. A LCD device is also provided.