GOA Gate Driving Circuit Using Shared Nodes for Compact Layouts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing gate driving circuits for display panels, particularly those using Gate Driver on Array (GOA) technology, face complexity in circuit structure, large layout size, and intricate timing due to the independent nodes in shift register units, which complicates the design and increases production costs.
Innovation Solution
A gate driving circuit with M groups of shift register units, each comprising N shift register units, where each group includes one first shift register unit and N-1 second shift register units, sharing a common second node and input signals, and featuring noise reduction circuits to simplify the circuit structure and reduce transistor count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If independent nodes are used in each shift register unit, then the circuit can function independently, but the circuit structure becomes complex and layout size increases
Solution Approach 1:
The patent merges the second nodes of multiple shift register units into a shared common node. Specifically, multiple second shift register units share the same second node, which reduces the total number of nodes in the circuit. This merging approach maintains the functional independence of each shift register unit while significantly simplifying the overall circuit structure and reducing layout area.
Solution Approach 2:
The shared second node serves multiple functions simultaneously: it acts as the control node for multiple second shift register units, provides a common reference potential, and enables coordinated operation across different groups. This multi-functional design reduces circuit complexity while maintaining reliable operation of all shift register units.
2Adaptability or versatility
If more shift register units are added to increase display resolution, then display quality improves, but circuit layout size increases
Solution Approach 1:
The patent organizes shift register units into groups where multiple units share common nodes and control signals. By merging the second nodes of N-1 second shift register units into a single shared node, the circuit achieves higher display resolution without proportionally increasing layout area. This grouping strategy allows scalable resolution improvement while controlling circuit footprint.
Solution Approach 2:
The circuit is segmented into M groups of shift register units, with each group containing N units that share common resources. This segmentation allows the circuit to be scaled by adjusting M and N independently, enabling resolution adaptation without linearly increasing overall circuit complexity and layout area.
3Manufacturing precision
If complex circuit structure is used to achieve precise timing control, then timing accuracy improves, but manufacturing cost increases
Solution Approach 1:
By merging multiple second nodes into a shared common node, the patent reduces the total component count and simplifies the circuit structure. This simplification directly lowers manufacturing complexity and production costs while the shared node architecture maintains precise timing control through coordinated signal distribution to all connected shift register units.
Data Source
AI summary
A gate driving circuit and a method for driving a gate driving circuit, a display panel, and a display device are provided. The gate driving circuit includes M groups of shift register units, and each group includes one first shift register unit and N−1 second shift register units. The first noise reduction of the first shift register unit performs noise reduction under control of the second node. The second noise reduction circuit of the second shift register units performs noise reduction under control of the second node. In a same group of shift register units, the first shift register unit and the second shift register units share a same second node. A first input signal and a second input signal received by a Kth group of shift register units are a shift signal of a first shift register unit in a (K−2)th group of shift register units.