GOA Inverter With Test Transistors for Single Mask Sizing
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Solution Overview
Problem
The conventional gate driver on array (GOA) circuit faces challenges in maintaining the correct waveform output due to varying transistor sizes, which can lead to shifted threshold voltages and reduced transistor performance over time, making it costly and inefficient to examine different size arrangements through multiple mask manufacturing.
Innovation Solution
The proposed solution includes an inverter with a first, second, third, and fourth transistor, along with first, second, and third test transistors, connected in a specific configuration to allow for examination of various size arrangements through control signals, enabling the inverter to be manufactured with a single mask, thereby reducing examination costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple masks are used to manufacture inverters with different size arrangements, then various transistor size configurations can be examined, but manufacturing costs increase significantly
Solution Approach 1:
The patent implements a universal test signal line that can be electrically connected to different transistor gates through switching elements, allowing a single mask design to test multiple transistor size arrangements. This multi-functional approach enables the same physical infrastructure to examine various inverter configurations without requiring separate masks for each arrangement.
Solution Approach 2:
The patent introduces dynamic reconfigurability through switching elements that can dynamically connect the test signal line to different transistor gates during operation. This dynamic switching capability allows the system to adapt between different transistor size arrangements on-the-fly, transforming a static manufacturing process into a dynamic, reconfigurable testing system that reduces mask requirements.
2Productivity
If transistor sizes are varied in the inverter, then different workload distributions can be achieved, but threshold voltage shifts occur and transistor performance degrades over time
Solution Approach 1:
The patent systematically varies transistor size parameters (width and length) to achieve different workload distributions while monitoring the effects on threshold voltage and performance stability. By changing these physical parameters in a controlled manner and using the test signal line to measure electrical characteristics, the invention identifies optimal size arrangements that balance productivity improvements with long-term reliability.
Solution Approach 2:
The patent implements a feedback mechanism where the test signal line measures the electrical characteristics of transistors with different size arrangements, providing data on threshold voltage shifts and performance degradation. This feedback information is used to evaluate and select transistor size configurations that maintain reliability while achieving desired workload distribution, allowing designers to make informed decisions about optimal transistor sizing.
Data Source
AI summary
An inverter, a gate driver on array circuit, and a display panel are provided. The inverter includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first test transistor, a second test transistor, and a third test transistor. A gate and a source of the first transistor and a source of the third transistor are electrically connected to a first test signal line, a drain of the first transistor, a drain of the second transistor is electrically connected to a first node, a gate of the second transistor and a gate of the fourth transistor are electrically connected to the pull-up node, and a drain of the third transistor and a drain of the fourth transistor are electrically connected to a second node.