GOA Circuit Stability via Ninth TFT Node P(n) Control

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Solution Overview

Problem

Conventional gate driver on array (GOA) circuits based on low temperature poly-silicon (LTPS) semiconductor TFTs face stability issues due to threshold voltage shift in the fourth and seventh transistors (T4 and T7) caused by prolonged operation, leading to abnormal output and decreased circuit stability.

Innovation Solution

The introduction of a ninth TFT in the GOA circuit, which controls the second node P(n) to switch between high and low voltage levels, preventing it from maintaining a constant high voltage level and thus mitigating the threshold voltage shift problem, enhancing the overall stability of the circuit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the fourth and seventh transistors (T4 and T7) operate continuously to maintain the second node P(n) at high voltage level, then the output terminal G(n) can maintain stable low voltage level, but the transistors experience threshold voltage shift over time leading to decreased circuit stability

Engineering Contradiction:
Improvecircuit stabilityVSAvoidoperation duration of T4 and T7
Core Design Contradiction:
ReliabilityVSDuration of action of moving object

Solution Approach 1:

The patent introduces a ninth TFT that periodically switches the second node P(n) between high and low voltage levels. Instead of continuous operation, the node is updated at specific timing intervals (during precharge phase and after output phase), allowing T4 and T7 to operate intermittently rather than continuously, thus preventing threshold voltage shift while maintaining output stability

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The ninth TFT creates a feedback mechanism that monitors the state of the second node P(n) and actively controls it to switch between high and low voltage levels. This feedback loop ensures that the node is updated at appropriate timing moments, preventing continuous operation of T4 and T7 while maintaining the stability of the output terminal G(n)

Inventive Principle:
Principle #23Feedback

2Reliability

If the second node P(n) is kept at constant high voltage level to ensure stable output, then the output terminal G(n) maintains low voltage level stability, but the constant voltage condition causes threshold voltage shift in T4 and T7

Engineering Contradiction:
Improveoutput stabilityVSAvoidvoltage level stability of P(n)
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The patent transforms the static constant high voltage condition of node P(n) into a dynamic state that alternates between high and low voltage levels. The ninth TFT controls this dynamic switching at specific timing moments (precharge phase and after output phase), allowing the node to be high when needed for stability and low when needed to prevent threshold voltage shift, thus achieving both output stability and transistor protection

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the voltage level parameter of node P(n) from a constant high value to a time-dependent parameter that switches between high and low. This parameter change is controlled by the ninth TFT at specific timing intervals, enabling the system to benefit from both high voltage stability and low voltage threshold protection at different operational stages

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10126621B2Gate driver on array circuit based on low temperature poly-silicon semiconductor thin film transistors
Publication Date: 2018.11.13 WUHAN CHINA STAR OPTOELECTRONICS TECH CO LTD
  • US10126621B2 patent drawing
  • US10126621B2 patent drawing
  • US10126621B2 patent drawing

AI summary

The present disclosure proposes a GOA circuit based on LTPS TFTs. A ninth TFT is introduced to adjust the high and low voltage levels imposed on the second node P(n). The ninth TFT includes a gate and a source both electrically connected to the second node P(n) and a drain electrically connected to a second clock signal. Such designs make it possible that the level of the second node P(n) is pulled down according to a certain frequency when an output terminal G(n) keeps the low voltage level. So the second node P(n) does not need to keep the high voltage level all the time in the present invention. Also, the fourth and the seventh transistors T4 and T7 do not have the problem of a threshold voltage shift due to a long working time.