GOA Protection Circuit for ESD and EOS Mitigation
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Solution Overview
Problem
The gate driver on array (GOA) unit in display panels is vulnerable to electrical static discharge (ESD) and electrical over stress (EOS), leading to display abnormalities and potential damage, especially in ultra-thin electronic devices.
Innovation Solution
A protection circuit is introduced for the GOA unit, comprising voltage gating modules and protection modules that adjust the gate driving signal voltages to clamp them within a safe range, using diodes and capacitors to absorb or release ESD/EOS energy, ensuring the gate driving signal remains within predetermined high and low voltage limits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the GOA unit is integrated at outside of display panel to reduce manufacturing complexity, then the device structure becomes simpler and manufacturing is easier, but the GOA unit becomes more vulnerable to ESD and EOS damage
Solution Approach 1:
The patent introduces a protection circuit as an intermediary component between the GOA unit and external environment. This protection circuit includes ESD protection elements and EOS protection elements that act as mediators to absorb or divert harmful electrical energy before it reaches the GOA unit, thereby resolving the vulnerability issue while maintaining the integrated external structure
2Area of stationary object
If the display panel area is increased to improve display quality, then the display performance is enhanced, but the GOA unit becomes more exposed to ESD influence
Solution Approach 1:
The patent segments the protection function into distinct protection circuits that can be distributed across the display panel. Each segment of the GOA unit or pixel array can have its own protection elements, allowing large area displays to be protected in a modular fashion that scales with the display size
3Reliability
If the GOA unit is made more robust against ESD and EOS by adding protection circuits, then the reliability is improved, but the device complexity increases
Solution Approach 1:
The patent merges the protection functions into compact integrated circuits that can be closely coupled with or integrated into the GOA unit. By combining multiple protection elements (ESD protection, EOS protection, voltage clamping) into a single integrated protection circuit, the solution improves reliability while minimizing the increase in device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The protection circuit effectively suppresses the impact of ESD/EOS on the gate driving signal, preventing damage to the TFTs and maintaining normal display functionality by keeping the gate driving signal within a specific voltage range, thus enhancing the reliability and quality of the display panel.
Implementation Method 1
using diodes and capacitors to absorb or release ESD/EOS energy
Implementation Method 2
ESD energy absorption and release mechanism
Data Source
AI summary
A protection circuit for a gate driver on array (GOA) unit, which relates to ESD or EOS protection for the gate GOA unit. The protection circuit includes: a first voltage gating module configured to output, when a gate line signal output end should output a valid driving voltage of a gate driving signal, an output voltage of an output end of a first voltage source; and a first protection module, an input end of which is connected to an output end of the first voltage gating module, and an output end of which is connected to a gate line; wherein in the case where the output voltage of the first voltage source and a current output voltage of the gate line signal output end satisfies a first predetermined condition, the first protection module outputs the output voltage of the output end of the first voltage source as an adjusted gate driving signal.