GOA Circuit Pull-Down Leakage Mitigation
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Solution Overview
Problem
Conventional gate driver on array (GOA) circuits experience electrical leakage due to threshold voltages less than 0V in oxide semiconductor thin film transistors, affecting the display performance of liquid crystal displays.
Innovation Solution
A GOA circuit with multi-level connected units and high-frequency clock signals is designed, featuring a pull-down unit with a single TFT and improved pull-up and pull-down control units to manage electrical potential, reducing leakage by maintaining the pull-down point at a low potential during non-charging states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If oxide semiconductor thin film transistors are used in GOA circuits, then good electrical properties are achieved, but threshold voltage becomes less than 0V causing electrical leakage
Solution Approach 1:
The patent changes the electrical parameters of the pull-down unit by introducing a holding capacitor to maintain the gate-source voltage at 0V, preventing the transistor from entering the on-state and eliminating electrical leakage caused by negative threshold voltage
Solution Approach 2:
The patent introduces a holding capacitor as an intermediary element between the pull-down TFT and the output node to maintain the electrical potential and prevent leakage, acting as a mediator that stabilizes the voltage state
2Device complexity
If conventional pull-down control units are used, then circuit structure is simple, but electrical leakage phenomenon is obvious
Solution Approach 1:
The patent applies preliminary action by pre-charging the holding capacitor to a specific voltage level before the actual signal transmission, ensuring that the pull-down TFT gate-source voltage is maintained at 0V to prevent leakage from occurring in the first place
Data Source
AI summary
A gate driver on array circuit and a liquid crystal display device are disclosed. The Nth-level GOA unit comprises: a pull-down unit; the pull-down unit comprises a first thin film transistor (TFT) which is connected to the input end of the (n+2)th-level high-frequency clock signal and a pull-down control unit respectively; the first TFT, a pull-up unit and a pull-up control unit are commonly connected to the pull-down point so as to pull-down the electrical potential of the pull-down point, wherein N is a positive integer greater than 3; n is positive integer.