GOA Circuit Reset Mechanism for Q Node Discharge
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Solution Overview
Problem
Existing Gate Driver on Array (GOA) circuits face challenges in completely discharging electric charge at the Q node during abnormal shutdown of LCD panels, requiring time to raise the reference voltage, which is not compatible with all driving systems.
Innovation Solution
Incorporating a reset circuit with its input terminal connected to the node between the pull-up control and pull-up circuits, and applying a high-level activation signal STV to the reset circuit's control terminal at shutdown to bring down the node's level, ensuring complete discharge without relying on the time required to raise the reference voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the reference voltage is raised to discharge the Q node, then the electric charge at the Q node can be completely discharged, but it requires time to raise the voltage to a high level which is not compatible with all driving systems
Solution Approach 1:
Instead of raising the reference voltage to discharge the Q node (conventional approach), the patent inverts the approach by pulling the Q node down to the reference voltage level through the reset circuit. This is achieved by activating the reset circuit with a first activation signal that connects the Q node to ground through a reset switch, rapidly discharging the node without requiring voltage ramping time.
Solution Approach 2:
The reset circuit is designed to be activated at the instant of shutdown before any other discharge mechanisms are engaged. By applying the first activation signal to the reset circuit at shutdown, the Q node is immediately discharged to reference voltage level, ensuring complete discharge occurs in advance of any potential abnormal startup conditions.
2Reliability
If the reference voltage is raised to discharge the Q node, then the electric charge at the Q node can be completely discharged, but the complexity of the driving system increases as it requires specially engineered timing
Solution Approach 1:
The patent simplifies the driving system by inverting the discharge mechanism from voltage-raising to voltage-pulling. The reset circuit with its switch connected between the Q node and reference voltage provides a direct discharge path that does not require complex timing engineering or system-specific voltage ramping sequences, making it universally compatible with different driving systems.
Solution Approach 2:
The patent extracts the discharge function into a separate, dedicated reset circuit that operates independently of the main reference voltage generation and control logic. This isolation allows the reset circuit to be activated by a simple first activation signal without interfering with or requiring coordination with other driving system components, reducing overall system complexity.
Data Source
AI summary
The present disclosure is about a Gate Driver on Array (GOA) circuit, its driving method, and a display panel employing the circuit. The GOA circuit has a node between its pull-up control circuit and pull-up circuit where a reference voltage is introduced. A reset circuit has its input terminal connected to the node, its output terminal connected to the reference voltage and its control terminal is applied an activation signal STV at the instant when the display panel is shutdown so as to bring down the node's level.