GOA Array Substrate Routing for Uniform Clock Line Capacitance
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Solution Overview
Problem
In display technologies, differences in resistance and capacitance between adjacent clock signal lines cause variations in scanning signal waveforms, leading to periodic horizontal dense lines on the display panel due to uneven lateral capacitance and resistance.
Innovation Solution
The design of an array substrate with a winding area between clock signal lines and GOA units, where communication lines are bent to ensure equal lateral capacitances, addressing the inconsistency in resistances and capacitances across different rows by equalizing the lengths and spacings of communication lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If clock signal lines are arranged in sequence from inside to outside, then the signal transmission path is established, but differences in resistance and capacitance between adjacent clock signal lines cause waveform variations and display defects
Solution Approach 1:
The patent applies parameter changes by adjusting the routing paths of communication lines to compensate for the inherent differences in resistance and capacitance of clock signal lines. Specifically, communication lines corresponding to outer clock signal lines (e.g., CK8) are routed to be closer to the GOA unit, while inner clock signal lines (e.g., CK1) have longer routing paths, thereby equalizing the total electrical characteristics across all clock signal lines and eliminating waveform variations
Solution Approach 2:
The patent employs asymmetry by deliberately creating unequal routing lengths and configurations for different communication lines. Instead of treating all communication lines equally, the design assigns asymmetric paths where outer clock signal lines have shorter communication line segments and inner clock signal lines have longer segments, compensating for the asymmetric electrical characteristics of the clock signal lines themselves
2Manufacturing precision
If existing winding compensation method is used, then resistance and capacitance differences are compensated, but lateral capacitance is increased that does not exist originally
Solution Approach 1:
The patent applies local quality by making different parts of the communication line structure have different characteristics. Specifically, the communication lines corresponding to different clock signal lines have different routing configurations - outer clock signal lines have communication lines routed closer to the GOA unit while inner clock signal lines have communication lines routed farther away, creating locally optimized electrical characteristics for each position
Solution Approach 2:
The patent inverts the conventional approach by not using uniform winding compensation for all clock signal lines. Instead of applying the same compensation method everywhere, it reverses the expected pattern by making outer clock signal lines have shorter communication paths and inner clock signal lines have longer paths, achieving compensation through inverse differential routing
Data Source
AI summary
An array substrate and a display panel are provided. The array substrate provided in the embodiments of the present disclosure includes a plurality of gate on array (GOA) units, a plurality of clock signal lines, and a plurality of communication lines. A winding area is provided between the clock signal lines and the GOA units. The communication lines are bent in the winding area. By means of the winding design, lateral capacitances of the communication lines that are on a same side are caused to be same. In this way, the problem that the lateral capacitances generated by the communication lines in different rows and surrounding traces are different is resolved.