GOA Circuit Segmentation for OLED Brightness Uniformity

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Solution Overview

Problem

Existing OLED display panels face issues with brightness gradation and macro display mura due to signal line loading, where gate drive signals become shorter in duration as they travel longer distances, leading to inconsistent pixel illumination.

Innovation Solution

The display panel design includes a substrate with a display region and a GOA region, featuring gate lines, a first GOA circuit with cascaded shift register units distributed on both sides of the substrate, and pixel groups coupled to gate lines in a manner that balances signal loading across rows.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If all shift register units are disposed on one side of the pixels, then the device complexity is reduced and manufacturing is simplified, but brightness uniformity deteriorates due to signal line loading effects

Engineering Contradiction:
ImproveGOA circuit layout complexityVSAvoidpixel brightness uniformity
Core Design Contradiction:
Device complexityVSIllumination intensity

Solution Approach 1:

The shift register units are segmented into two groups: first shift register units disposed on a first side of the pixels and second shift register units disposed on a second side of the pixels. This segmentation balances the signal line loading on both sides, ensuring uniform gate drive signal duration across all pixel rows and eliminating brightness non-uniformity while maintaining manageable device complexity through systematic arrangement.

Inventive Principle:
Principle #1Segmentation

2Area of stationary object

If gate drive signals are transmitted over long distances, then the display area can be larger, but the signal duration becomes shorter leading to brightness gradation

Engineering Contradiction:
Improvedisplay areaVSAvoidgate drive signal duration
Core Design Contradiction:
Area of stationary objectVSDuration of action of moving object

Solution Approach 1:

By dividing the shift register units into two groups positioned on opposite sides of the pixel array, the signal transmission paths are balanced in length. This allows the display area to be extended while maintaining consistent signal duration across all rows, as each row receives signals from both sides with comparable path lengths, preventing brightness gradation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different arrangements of shift register units to different regions (first side and second side) of the pixel array. Each region's shift register units are configured to compensate for the specific signal transmission distance to that region, ensuring that local signal characteristics are optimized for uniform brightness across the entire large display area.

Inventive Principle:
Principle #3Local quality

3Device complexity

If signal line loading is not balanced, then the circuit design is simpler, but macro display mura occurs due to inconsistent pixel illumination

Engineering Contradiction:
Improvecircuit design complexityVSAvoidmacro display mura
Core Design Contradiction:
Device complexityVSObject-affected harmful factors

Solution Approach 1:

The shift register units are segmented into first and second groups disposed on opposite sides of the pixels. This segmentation creates balanced signal line loading on both sides of the display, ensuring that all pixel rows experience similar total capacitance and resistance loads. This balance eliminates the macro display mura effect caused by inconsistent signal attenuation while maintaining straightforward circuit design through symmetrical arrangement.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12211450B2Display panel and display device
Publication Date: 2025.01.28 CHENGDU BOE OPTOELECTRONICS TECH CO LTD
  • US12211450B2 patent drawing
  • US12211450B2 patent drawing
  • US12211450B2 patent drawing

AI summary

A display panel and a display device are provided, which belong to the field of display technologies. The display panel includes: a substrate including a display region and a gate driver on array (GOA) region, a plurality of rows and a plurality of columns of pixels disposed in the display region, and a first GOA circuit disposed in the GOA region. The first GOA circuit includes a plurality of cascaded first shift register units, and the plurality of first shift register units are coupled to the plurality of rows of pixels by a plurality of gate lines, and are configured to transmit gate drive signals to the plurality of rows of pixels through the plurality of gate lines, to drive the plurality of rows of pixels to emit light.