Gate Driver on Array Circuit Shared Pull-Down Transistors

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Solution Overview

Problem

Conventional gate driver on array (GOA) circuits in TFT-LCDs have a high number of transistors and capacitors, leading to increased parasitic capacitance charging and discharging, which consumes more power, especially with high-frequency clock signals.

Innovation Solution

The GOA circuit is designed with GOA circuit units coupled in cascade, sharing pull-down circuits and using a specific configuration of transistors and clock signals to reduce the number of transistors and lower clock signal frequencies, thereby decreasing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional GOA circuit units are used with separate pull-down circuits, then each circuit unit can independently control scanning signals, but the number of transistors and capacitors increases, leading to higher parasitic capacitance and power consumption

Engineering Contradiction:

Improveindependent control capabilityVSAvoidnumber of transistors and capacitors

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the pull-down circuits of adjacent GOA circuit units by sharing the third transistor (T3) and third capacitor (C3) between two consecutive units. This combining approach reduces the total number of transistors and capacitors while maintaining the independent control capability of each GOA circuit unit through the preserved first transistor (T1), second transistor (T2), and their associated capacitors.

Inventive Principle:

Principle #5Merging (Combining)

2Ease of operation

If more transistors and capacitors are used in each GOA circuit unit, then better signal control is achieved, but parasitic capacitance increases and power consumption rises

Engineering Contradiction:

Improvesignal control capabilityVSAvoidpower consumption

Core Design Contradiction:

Ease of operationVSLoss of energy

Solution Approach 1:

By combining pull-down circuits between adjacent GOA circuit units through shared transistors and capacitors, the patent reduces the total parasitic capacitance in the system. This reduction directly lowers power consumption while the retained control transistors and capacitors maintain adequate signal control capability.

Inventive Principle:

Principle #5Merging (Combining)

3Speed

If clock signal frequency is increased, then scanning speed improves, but power consumption from parasitic capacitance charging and discharging increases significantly

Engineering Contradiction:

Improvescanning speedVSAvoidpower consumption from parasitic capacitance

Core Design Contradiction:

SpeedVSLoss of energy

Solution Approach 1:

The patent reduces the total parasitic capacitance by merging pull-down circuits between adjacent GOA circuit units. This reduction in parasitic capacitance decreases the energy required for charging and discharging during each clock cycle, thereby lowering power consumption while allowing higher clock frequencies to maintain scanning speed.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS9786242B2Gate driver on array circuit and display using the same

Publication Date: 2017.10.10 WUHAN CHINA STAR OPTOELECTRONICS TECH CO LTD

AI summary

A GOA circuit includes GOA circuit units. The GOA circuit units at every two stages share a pull-down circuit. The pull-down circuit includes a first transistor, a second transistor and a third transistor. The present invention uses fewer transistors for the GOA circuit and lower the frequency of the first and second clock signals. The decrease in the frequency of the first and second clock signals helps a decrease in the frequency of charge and discharge to the parasitic capacitance and further a reduction in overall power consumption of the GOA circuit.