GOA Shift Register Circuit for Narrow-Bezel Low-Power Displays
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Solution Overview
Problem
GOA circuits in display devices occupy a large area and result in high power consumption, hindering the realization of narrow bezels and efficient display performance.
Innovation Solution
A shift register design incorporating a pull-up control sub-circuit, pull-down control sub-circuit, output sub-circuit, noise reduction sub-circuit, and reset sub-circuit, along with a gate driving circuit that includes cascaded shift registers, to manage signal transmission and reduce noise, thereby optimizing display performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If GOA circuits are arranged on both sides of the effective display region to enable high resolution and narrow bezels, then display performance is improved, but the occupied area and power consumption increase
Solution Approach 1:
The patent merges the pull-up and pull-down control functions into a single integrated control structure where the pull-up control sub-circuit and pull-down control sub-circuit share common nodes and control signals. This integration reduces the overall area occupied by the GOA circuit while maintaining the necessary functionality for driving gate lines in high-resolution displays with narrow bezels.
Solution Approach 2:
The control nodes in the patent serve multiple functions simultaneously. For example, the first control node and second control node are used for both signal transmission and noise reduction through the coupled noise reduction sub-circuit. This multi-functionality reduces the number of dedicated components needed, thereby reducing the occupied area while maintaining display performance.
2Reliability
If GOA circuits are arranged on both sides of the effective display region to enable high resolution and narrow bezels, then display performance is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic control of the pull-up and pull-down sub-circuits through clocked operation. The pull-up control sub-circuit and pull-down control sub-circuit are activated in alternating or coordinated periods based on the driving signal requirements, rather than remaining continuously active. This periodic operation reduces average power consumption while maintaining the ability to drive gate lines for high-resolution displays with narrow bezels.
Solution Approach 2:
The coupled noise reduction sub-circuit provides feedback mechanisms that monitor the state of control nodes and adjust the operation of pull-up and pull-down sub-circuits accordingly. This feedback ensures that power is consumed only when necessary for signal transmission and noise reduction, optimizing power efficiency while maintaining display performance in high-resolution narrow-bezel displays.
3Reliability
If noise reduction sub-circuit is added to manage signal transmission, then signal stability is improved, but device complexity increases
Solution Approach 1:
The noise reduction sub-circuit is merged with the existing pull-up and pull-down control sub-circuits by sharing control nodes and signal pathways. The first noise reduction sub-circuit couples the first control node with the second control node, and the second noise reduction sub-circuit couples the third control node with the fourth control node. This merging approach provides noise reduction functionality without adding completely separate circuit blocks, thereby limiting the increase in device complexity while improving signal stability.
Data Source
AI summary
A shift register and a driving method therefor, a gate driving circuit and a display device are provided, wherein the shift register includes a pull-up control sub-circuit configured to provide a signal of a first signal terminal or a second signal terminal to a pull-up control node under control of a first input terminal and a second output terminal; the pull-down control sub-circuit is configured to provide a signal of a first power supply terminal or a second power supply terminal to a pull-down node under control of the pull-up control node, the first signal terminal, the second signal terminal, a first clock signal terminal and a second clock signal terminal; the output sub-circuit is configured to supply a signal of a third clock signal terminal to a first output terminal and a signal of a fourth clock signal terminal to the second output terminal.