GOA Shift Register Unit for Dual-Direction Scanning Stability
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Solution Overview
Problem
In Gate Driver On Array (GOA) circuits with dual-direction scanning, the stress on input transistors during forward and reverse scanning differs, leading to negative offset of threshold voltage, causing electric leakage and a no-output phenomenon, especially in oxide transistor-based circuits like those using indium gallium zinc oxide (IGZO), which are prone to instability.
Innovation Solution
A shift register unit is designed with an input circuit that controls the pull-up node level in response to an input signal, a pull-up node reset circuit to reset the pull-up node, and an output circuit to output a clock signal, along with noise reduction circuits to maintain transistor bias and prevent leakage, allowing for reliable dual-direction scanning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dual-direction scanning is implemented in GOA circuits, then scanning flexibility is improved, but transistor threshold voltage offset and electric leakage increase
Solution Approach 1:
The patent applies preliminary action by introducing a pull-up node reset circuit that proactively resets the pull-up node before it may accumulate threshold voltage offset. The reset circuit includes a reset transistor that can be activated in advance to restore the pull-up node to its initial state, preventing the accumulation of offset during subsequent scanning operations. This preliminary reset action ensures the transistor maintains stable threshold voltage characteristics when switching between forward and reverse scanning modes.
Solution Approach 2:
The patent uses an intermediary approach by introducing a pull-up node as a mediator between the input signal and the transistor gate. The pull-up node acts as a buffer that can be independently controlled and reset, separating the scanning control function from the transistor driving function. This intermediary structure allows the system to maintain stable transistor operation while implementing flexible dual-direction scanning, as the pull-up node can be reset without affecting the transistor's threshold voltage characteristics.
2Ease of manufacture
If oxide transistors are used in GOA circuits, then manufacturing cost is reduced, but circuit stability deteriorates
Solution Approach 1:
The patent applies preliminary action by implementing a reset circuit that proactively compensates for oxide transistor instability before it affects circuit operation. The reset transistor is configured to reset the pull-up node in advance, preventing threshold voltage offset accumulation that is particularly problematic in oxide transistors. This preliminary reset action stabilizes the circuit operation and prevents the no-output phenomenon that oxide transistors are prone to experiencing during dual-direction scanning.
Solution Approach 2:
The patent implements feedback by creating a control mechanism that monitors and adjusts the pull-up node state based on circuit operation conditions. The reset circuit is activated when threshold voltage offset is detected or anticipated, providing feedback control to maintain stable transistor operation. This feedback mechanism compensates for the inherent instability of oxide transistors, ensuring reliable circuit operation while maintaining the manufacturing cost advantages of using oxide transistor-based GOA circuits.
Data Source
AI summary
A shift register unit, a method of driving a shift register unit, a gate driving circuit and a display device are provided. The shift register unit includes an input circuit, a first pull-up node reset circuit and an output circuit. The input circuit is configured to control an level of a pull-up node to a first level in response to an input signal of an input terminal, and thereafter control a level of a first node to a second level under control of a level of a pull-down node. The first node is in a current path for controlling the level of the pull-up node. The first pull-up node reset circuit is configured to reset the pull-up node in response to a first reset signal. The output circuit is configured to output a clock signal to an output terminal under control of the level of the pull-up node.