GOA Shift Register Layout for Faster Gate Signal Fall Time
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Solution Overview
Problem
Existing GOA circuits face challenges in achieving high refresh rates and reducing border width in large-sized display devices due to the limitations of odd-even interlace driving mode, which prolongs the falling time of gate driving signals, making it difficult to meet market demands for low-cost, narrow bezel, and lightweight designs.
Innovation Solution
The display substrate incorporates a shift register with an input circuit, an output circuit, and first and second output pull-down circuits, connected to a power voltage line, to reduce the falling time of gate driving signals at both ends of the gate lines, utilizing an odd-even interlace driving mode to minimize border width and maintain high resolution and refresh rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If odd-even interlace driving mode is used in GOA circuits, then border width is reduced and costs are lowered, but the falling time of gate driving signals is prolonged
Solution Approach 1:
The gate driving signal output terminal is divided into two separate output terminals, allowing independent control of signal output at different ends of the gate line. This segmentation enables asymmetric driving where each end can be optimized independently, reducing the falling time contradiction while maintaining narrow border width benefits of odd-even interlace mode
Solution Approach 2:
Different output terminals are provided with different signal levels through independent control circuits. The local quality principle allows the gate driving signal to have optimized characteristics at each end of the gate line, specifically reducing falling time at critical regions while maintaining the overall narrow border width advantage of the odd-even interlace driving mode
2Loss of time
If additional output pull-down circuits are added to reduce falling time, then signal falling time is reduced, but device complexity increases
Solution Approach 1:
The output pull-down circuits are merged with the existing shift register structure by sharing common components such as power voltage lines, control terminals, and transistor elements. This integration approach reduces the additional complexity that would normally arise from adding separate pull-down circuits, as they are combined into the existing gate driving circuit architecture
Solution Approach 2:
The output pull-down circuits are designed to serve multiple functions: they reduce the falling time of gate driving signals, provide signal level adjustment, and integrate with the odd-even interlace driving mode control. This multi-functionality reduces the need for separate dedicated circuits, thereby limiting the increase in device complexity while achieving the desired signal timing improvement
Data Source
AI summary
A display substrate and a display device are provided. The display substrate includes a shift register including an input circuit, an output circuit, a first output pull-down circuit, and a second output pull-down circuit. The input circuit is configured to respond to a first drive signal on a control terminal of the input circuit to write an input signal on an input terminal of the input circuit into a first node. The output circuit is configured to respond to a signal on the first node to output a clock signal as a gate driving signal through an output terminal of the output circuit. The first and second output pull-down circuits are configured to reduce the falling time of the gate driving signals at two ends of a gate line.