GOA Shift Register Parallel Driving Circuit
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Solution Overview
Problem
Gate Driver On Array (GOA) technology experiences significant signal delay in scanning signal output, leading to increased time for driving the gate line by line, which results in higher panel resolution requirements.
Innovation Solution
A circuit and method that include multiple scanning lines, clock signal connecting lines, and shift register units in cascade, where adjacent shift register units receive clock signals with the same waveform, allowing two scanning lines to be driven simultaneously, thereby reducing charging time and panel resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If GOA circuit is used for gate driving, then the scanning signal can be generated on the array substrate, but the signal delay is large which increases the time for driving gate line by line
Solution Approach 1:
The patent divides the gate driving task into multiple parallel segments by grouping shift register units. Specifically, multiple shift register units share common clock signal lines, allowing them to operate simultaneously on different gate lines. This segmentation enables parallel processing of gate scanning across multiple lines, reducing the overall time required and mitigating the signal delay inherent in sequential GOA operation.
2Device complexity
If gate lines are driven sequentially line by line, then the circuit structure is simple, but the time cost for driving increases and panel resolution requirements increase
Solution Approach 1:
The patent merges multiple shift register units by having them share common clock signal lines (first clock signal line and second clock signal line). This merging allows multiple gate lines to be driven in parallel using a unified clocking scheme, reducing the driving time without significantly increasing circuit complexity. The shared clock lines enable synchronized operation of multiple shift register units while maintaining a relatively simple overall circuit structure.
3Productivity
If more clock signal lines are used to drive more scanning lines in parallel, then the charging time is reduced, but the device complexity increases
Solution Approach 1:
The patent implements multi-functionality by having clock signal lines serve multiple purposes. The first clock signal line and second clock signal line are shared by multiple shift register units, allowing a limited number of clock lines to control a larger number of gate lines. This universal usage of clock signal lines enables parallel driving of multiple scanning lines while avoiding the need to increase the number of clock lines proportionally, thus maintaining acceptable device complexity while improving charging speed.
Data Source
AI summary
Provided are a circuit, a method of driving the panel, and a display device. The driving circuit includes a plurality of scanning lines, a plurality of clock signal connecting lines, a time controller and a multiple shift register unit. The input end of the shift register unit is correspondingly connected to the other end of the clock signal connecting line to receive clock signals of the time controller, and the output ends of the shift register units are connected with the scanning lines in one-to-one correspondence; Starting from the first shift register unit, the adjacent two shift register units are taken as a shift register group, and the clock signals sent by the time controller to the two shift register units in the same group via the clock signal connecting line have the same waveform.