GOA Signal Bus Segmentation for Display Panel
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Solution Overview
Problem
Current GOA-in-source technologies experience signal delays and waveform differences across the GOA signal bus, leading to poor charging of pixels in display areas due to large-area crossings of the GOA signal bus and data wires, especially near and far access points.
Innovation Solution
A display panel design with a GOA circuit and signal bus in the wide-area, parallel to the main display area, featuring thin-film chips with output terminals connected by metal wiring, reducing signal differences by rearranging signal outputs from both sides of the chip-on-film area to outputs from each thin-film chip, and using parallel signal wirings with connecting wirings to minimize delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the GOA signal bus crosses data wires in a large-area configuration, then the GOA circuit can be integrated on the panel, but signal delays and waveform differences occur due to RC loading
Solution Approach 1:
The patent segments the GOA signal bus into multiple separate signal lines (first GOA signal line, second GOA signal line, etc.) instead of using a single large-area bus. This segmentation reduces the crossing area with data wires, thereby reducing RC loading and waveform differences while maintaining GOA circuit integration benefits
Solution Approach 2:
The patent transitions from a planar large-area GOA signal bus to a multi-layered wiring structure where different GOA signal lines are arranged in different metal layers. This dimensional change allows signals to be routed without large-area crossings, reducing RC loading while maintaining signal distribution functionality
2Area of stationary object
If the GOA signal bus is configured to access both near and far regions, then the entire display area can be driven, but significant waveform delay differences occur between near-end and far-end access points
Solution Approach 1:
The patent divides the GOA signal distribution into multiple segmented signal lines, each serving specific regions. This segmentation allows optimized routing for different distances, reducing the cumulative RC loading effect on far-end signals while maintaining comprehensive display area coverage
Solution Approach 2:
The patent implements different signal line configurations for different regions: shorter routing for near-end access points and optimized multi-layer routing for far-end access points. This local optimization ensures uniform signal delay characteristics across the entire display area despite varying distances
3Reliability
If connecting wires are added to connect first and second signal wirings, then signal distribution to multiple thin-film chips is improved, but wiring complexity increases
Solution Approach 1:
The patent uses vertical connections through via holes in insulating layers to connect signal wirings in different metal layers. This three-dimensional wiring approach efficiently connects multiple thin-film chips without requiring complex planar wiring, improving signal distribution while controlling wiring complexity through systematic layering
Data Source
AI summary
A display panel and a spliced display panel are provided. The display panel includes a GOA circuit, a GOA signal bus, and a chip-on-film area. The present invention changes a traditional way that signal outputs from both sides of the chip-on-film area to a way that signal outputs from each thin-film chip, so as to reduce signal difference in wiring of a GOA bus.