GOA Signal Determining Circuit for Abnormal Output Prevention
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Solution Overview
Problem
In liquid crystal display (LCD) technology, the partial loss of GOA input signal during a single frame period leads to abnormal outputs, which existing reset devices cannot prevent due to the limitations of single pulse-based frame start and Tot-RST signals.
Innovation Solution
A GOA signal determining circuit that connects to the input end and clock signal ends of a GOA unit, detecting anomalies and outputting a control signal to a reset unit to turn off the output transistor, utilizing a NOR gate and transistors to ensure timely reset of the PU node, thereby preventing abnormal outputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a reset device is added to reset the PU node using single pulse-based STV or Tot-RST signals, then the GOA circuit can be reset at frame boundaries, but it cannot respond to partial signal loss occurring within a single frame period
Solution Approach 1:
The patent uses multiple clock signal ends (CLK1, CLK2, CLK3, CLK4) that operate in periodic cycles to continuously monitor the GOA input signal. By distributing monitoring across multiple periodic clock cycles, the system ensures that signal loss at any point in the frame period is detected, overcoming the limitation of single-pulse reset signals that only check at frame boundaries.
Solution Approach 2:
The patent implements a feedback mechanism where the state of multiple clock signal ends is continuously monitored and fed back to the reset device. The reset device activates when it detects that all clock signal ends are in the same state (indicating signal loss), creating a closed-loop system that responds dynamically to signal conditions rather than relying on predetermined single-pulse reset signals.
2Reliability
If multiple clock signal ends are monitored to detect signal loss, then coverage of signal loss detection is improved, but the device complexity increases
Solution Approach 1:
The patent merges the monitoring function into the existing clock signal distribution network. The same clock signals (CLK1-CLK4) that drive the GOA unit are also used for monitoring, eliminating the need for separate monitoring circuits. The reset device simply monitors the states of existing clock signal ends rather than adding independent monitoring infrastructure.
Solution Approach 2:
The clock signal ends serve dual functions: they drive the normal operation of the GOA unit and simultaneously serve as monitoring points for detecting signal loss. This multi-functionality reduces the need for additional dedicated monitoring components, thereby limiting the increase in device complexity while improving detection coverage.
Data Source
AI summary
A GOA signal determining circuit and method thereof, gate driver circuit, and display device are provided. The GOA signal determining circuit is connected to an input end of a GOA unit, at least two clock signal ends of the GOA unit, and a control end of a reset unit of a PU node in the GOA unit. The GOA signal determining circuit detects a signal of the input end of the GOA unit and a signal of the at least two clock signal ends of the GOA unit, and outputs a control signal to the reset unit of the PU node to control the reset unit to output a reset signal to the PU node to turn off an output transistor of the GOA unit, upon determining both of the signal of the input end and the signal of the at least two clock signal ends are abnormal.